Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 205 of 870
Sep 30, 2010
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set
value of the TPnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal (INTTPnCC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TPnCCR0 register + 1) × Count clock cycle
Remark n = 0 to 5
Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1 0 0 0 0
TPnCTL0
Select count clock
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TPnCKS2 TPnCKS1 TPnCKS0TPnCE
(b) TMPn control register 1 (TPnCTL1)
0 0 0/1
Note
00
TPnCTL1
0, 0, 0:
Interval timer mode
0: Operate on count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count with external
event count input signal
000
TPnMD2 TPnMD1 TPnMD0TPnEEETPnEST
Note This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and INTTPnCC1) are masked
by the interrupt mask flags (TPnCCMK0 and TPnCCMK1) and timer output (TOPn1) is performed at the
same time. However, set the TPnCCR0 and TPnCCR1 registers to the same value (see 7.5.1 (2) (d)
Operation of TPnCCR1 register).