Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 204 of 870
Sep 30, 2010
7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the
TPnCTL0.TPnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOPn0 pin.
Usually, the TPnCCR1 register is not used in the interval timer mode.
Figure 7-2. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer registerTPnCE bit
TPnCCR0 register
Count clock
selection
Clear
Match signal
TOPn0 pin
INTTPnCC0 signal
Remark n = 0 to 5
Figure 7-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
D 0
D 0 D 0 D 0 D 0
Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1) Interval (D 0 + 1)
Remark n = 0 to 5