Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 197 of 870
Sep 30, 2010
(6) TMPn option register 0 (TPnOPT0)
The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TPnCCS1
0
1
TPnCCR1 register capture/compare selection
The TPnCCS1 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TPnOPT0
(n = 0 to 5)
0 TPnCCS1 TPnCCS0 0 0 0 TPnOVF
654321
After reset: 00H R/W Address: TP0OPT0 FFFFF595H, TP1OPT0 FFFFF5A5H,
TP2OPT0 FFFFF5B5H, TP3OPT0 FFFFF5C5H,
TP4OPT0 FFFFF5D5H, TP5OPT0 FFFFF5E5H
TPnCCS0
0
1
TPnCCR0 register capture/compare selection
The TPnCCS0 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TPnOVF
Set (1)
Reset (0)
TMPn overflow detection flag
• The TPnOVF bit is set when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
• An interrupt request signal (INTTPnOV) is generated at the same time that the
TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TPnOVF bit is not cleared even when the TPnOVF bit or the TPnOPT0
register are read when the TPnOVF bit = 1.
• The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set
to 1 by software. Writing 1 has no influence on the operation of TMPn.
Overflow occurred
TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0
7 <0>
Cautions 1. Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE
bit = 0. (The same value can be written when the TPnCE
bit = 1.) If rewriting was mistakenly performed, clear the
TPnCE bit to 0 and then set the bits again.
2. Be sure to clear bits 1 to 3, 6, and 7 to “0”.