Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 193 of 870
Sep 30, 2010
0
TPnEST
0
1
Software trigger control
TPnCTL1
(n = 0 to 5)
TPnEST TPnEEE 0 0 TPnMD2 TPnMD1 TPnMD0
<6> <5> 4 3 2 1
After reset: 00H R/W Address:
TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H,
TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H,
TP4CTL1 FFFFF5D1H, TP5CTL1 FFFFF5E1H
Generate a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
1 to the TPnEST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with
writing 1 to the TPnEST bit as the
trigger.
Disable operation with external event count input.
(Perform counting with the count clock selected by the TPnCTL0.TPnCK0
to TPnCK2 bits.)
TPnEEE
0
1
Count clock selection
The TPnEEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
7 0
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
TPnMD2
0
0
0
0
1
1
1
1
Timer mode selection
TPnMD1
0
0
1
1
0
0
1
1
TPnMD0
0
1
0
1
0
1
0
1
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
−
Cautions 1. The TPnEST bit is valid only in the external trigger pulse output
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
2. External event count input is selected in the external event count
mode regardless of the value of the TPnEEE bit.
3. Set the TPnEEE and TPnMD2 to TPnMD0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the
TPnCE bit = 1.) The operation is not guaranteed when rewriting is
performed with the TPnCE bit = 1. If rewriting was mistakenly
performed, clear the TPnCE bit to 0 and then set the bits again.
4. Be sure to clear bits 3, 4, and 7 to “0”.