Datasheet

V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 192 of 870
Sep 30, 2010
(1) TMPn control register 0 (TPnCTL0)
The TPnCTL0 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TPnCTL0 register by software.
TPnCE
TMPn operation disabled (TMPn reset asynchronously
Note
).
TMPn operation enabled. TMPn operation started.
TPnCE
0
1
TMPn operation control
TPnCTL0
(n = 0 to 5)
0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0
654321
After reset: 00H R/W Address: TP0CTL0 FFFFF590H, TP1CTL0 FFFFF5A0H,
TP2CTL0 FFFFF5B0H, TP3CTL0 FFFFF5C0H,
TP4CTL0 FFFFF5D0H, TP5CTL0 FFFFF5E0H
<7> 0
f XX
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /32
f
XX /64
f
XX /128
f
XX /256
f
XX /512
TPnCKS2
0
0
0
0
1
1
1
1
Internal count clock selection
n = 0, 2, 4 n = 1, 3, 5
TPnCKS1
0
0
1
1
0
0
1
1
TPnCKS0
0
1
0
1
0
1
0
1
Note TPn0PT0.TPnOVF bit, 16-bit counter, timer output (TOPn0, TOPn1 pins)
Cautions 1. Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0.
When the value of the TPnCE bit is changed from 0 to 1, the
TPnCKS2 to TPnCKS0 bits can be set simultaneously.
2. Be sure to clear bits 3 to 6 to “0”.
Remark f
XX: Main clock frequency
(2) TMPn control register 1 (TPnCTL1)
The TPnCTL1 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.