Datasheet
V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
R01UH0015EJ0300 Rev.3.00 Page 189 of 870
Sep 30, 2010
7.3 Configuration
TMPn includes the following hardware.
Table 7-1. Configuration of TMPn
Item Configuration
Timer register 16-bit counter
Registers
TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1)
TMPn counter read buffer register (TPnCNT)
CCR0, CCR1 buffer registers
Timer inputs 2 (TIPn0
Note 1
, TIPn1 pins)
Timer outputs 2 (TOPn0, TOPn1 pins)
Control registers
Note 2
TMPn control registers 0, 1 (TPnCTL0, TPnCTL1)
TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2)
TMPn option register 0 (TPnOPT0)
Notes 1. The TIPn0 pin functions alternately as a capture trigger input signal, external event count input
signal, and external trigger input signal.
2. When using the functions of the TIPn0, TIPn1,TOPn0, and TOPn1 pins, see Table 4-15 Using
Port Pin as Alternate-Function Pin.
Remark n = 0 to 5
Figure 7-1. Block Diagram of TMPn
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
Note 1
, f
XX
/256
Note 2
f
XX
/128
Note 1
, f
XX
/512
Note 2
Selector
Internal bus
Internal bus
TOPn0
TOPn1
TIPn0
TIPn1
Selector
Edge
detector
CCR0
buffer
register
CCR1
buffer
register
TPnCCR0
TPnCCR1
16-bit counter
TPnCNT
INTTPnOV
INTTPnCC0
INTTPnCC1
Output
controller
Clear
Notes 1. TMP0, TMP2, TMP4
2. TMP1, TMP3, TMP5
Remark f
XX: Main clock frequency