Datasheet
V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 187 of 870
Sep 30, 2010
(4) PLL lockup time specification register (PLLS)
The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed
from 0 to 1.
This register can be read or written in 8-bit units.
Reset sets this register to 03H.
0
2
10
/f
X
2
11
f
X
2
12
/f
X
2
13
/f
X
(default value)
PLLS1
0
0
1
1
PLLS0
0
1
0
1
Selection of PLL lockup time
PLLS 0 0 0 0 0 PLLS1 PLLS0
After reset: 03H R/W Address: FFFFF6C1H
Cautions 1. Set so that the lockup time is 800
μ
s or longer.
2. Do not change the PLLS register setting during the lockup period.
6.5.3 Usage
(1) When PLL is used
• After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default
mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
• To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK
bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then
stop the PLL (PLLON bit = 0).
• The PLL stops during transition to the IDLE2 or STOP mode regardless of the setting and is restored from the
IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows.
(a) When transiting to the IDLE2 or STOP mode from the clock through mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 350
μ
s (min.) or longer.
(b) When transiting to the IDLE 2 or STOP mode while remaining in the PLL operation mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 800
μ
s (min.) or longer.
When transiting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary.
(2) When PLL is not used
• The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is
operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).