Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 186 of 870
Sep 30, 2010
(3) Lock register (LOCKR)
Phase lock occurs at a given frequency following power application or immediately after the STOP mode is
released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until
stabilization is called the lockup status, and the stabilized state is called the locked status.
The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
0LOCKR 0 0 0 00 0 LOCK
Locked status
Unlocked status
LOCK
0
1
PLL lock status check
After reset: 00H R Address: FFFFF824H
< >
Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear
conditions are as follows.
[Set conditions]
• Upon system reset
Note
• In IDLE2 or STOP mode
• Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0)
• Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of
PCC.MCK bit to 1)
Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the
oscillation stabilization time has elapsed.
[Clear conditions]
• Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 21.2
(3) Oscillation stabilization time select register (OSTS)))
• Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release,
when the STOP mode was set in the PLL operating status
• Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed
from 0 to 1
• After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register)
when the IDLE2 mode is set during PLL operation.