Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 185 of 870
Sep 30, 2010
(2) Clock control register (CKC)
The CKC register is a special register. Data can be written to this register only in a combination of specific
sequence (see 3.4.7 Special registers).
The CKC register controls the internal system clock in the PLL mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 0AH.
0CKC 0 0 0 1 0 1 CKDIV0
After reset: 0AH R/W Address: FFFFF822H
f XX = 4 × f X (f X = 2.5 to 5.0 MHz)
f
XX = 8 × f X (f X = 2.5 to 4.0 MHz)
CKDIV0
0
1
Internal system clock (f
XX ) in PLL mode
Cautions 1. The PLL mode cannot be used at fX = 5.0 to 10.0 MHz.
2. Before changing the multiplication factor between 4 and 8 by using the CKC register, set
the clock-through mode and stop the PLL.
3. Be sure to set bits 3 and 1 to “1” and clear bits 7 to 4 and 2 to “0”.
Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is
divided by the PCC register.