Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 184 of 870
Sep 30, 2010
6.5 PLL Function
6.5.1 Overview
In the V850ES/JG3, an operating clock that is 4 or 8 times higher than the oscillation frequency output by the PLL
function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions.
When PLL function is used (×4): Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz)
When PLL function is used (×8): Input clock = 2.5 to 4 MHz (output: 20 to 32 MHz)
Clock-through mode: Input clock = 2.5 to 10 MHz (output: 2.5 to 10 MHz)
6.5.2 Registers
(1) PLL control register (PLLCTL)
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
0PLLCTL 0 0 0 00 SELPLL PLLON
PLL stopped
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
PLLON
0
1
PLL operation stop register
Clock-through mode
PLL mode
SELPLL
0
1
CPU operation clock selection register
After reset: 01H R/W Address: FFFFF82CH
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Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
through mode).
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
(unlocked), “0” is written to the SELPLL bit if data is written to it.