Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 183 of 870
Sep 30, 2010
6.4 Operation
6.4.1 Operation of each clock
The following table shows the operation status of each clock.
Table 6-1. Operation Status of Each Clock
PCC Register
CLK Bit = 0, MCK Bit = 0
CLS Bit = 1,
MCK Bit = 0
CLS Bit = 1,
MCK Bit = 1
Register Setting and
Operation Status
Target Clock
During
Reset
During
Oscillation
Stabilization
Time Count
HALT
Mode
IDLE1,
IDLE2
Mode
STOP
Mode
Subclock
Mode
Sub-IDLE
Mode
Subclock
Mode
Sub-IDLE
Mode
Main clock oscillator (fX)
×
× × ×
Subclock oscillator (fXT)
CPU clock (fCPU)
× × × × ×
× ×
Internal system clock (fCLK)
× ×
× × × ×
Main clock (in PLL mode, fXX)
×
Note
× × × ×
Peripheral clock (fXX to fXX/1,024)
× ×
× × × × ×
WT clock (main)
× ×
× × ×
WT clock (sub)
WDT2 clock (internal oscillation)
×
WDT2 clock (main)
× ×
× × × × ×
WDT2 clock (sub)
Note Lockup time
Remark
: Operable
×: Stopped
6.4.2 Clock output function
The clock output function is used to output the internal system clock (f
CLK) from the CLKOUT pin.
The internal system clock (f
CLK) is selected by using the PCC.CK3 to PCC.CK0 bits.
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control
register of port CM.
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the clock
when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in the port
mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z.