Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 181 of 870
Sep 30, 2010
(b) Example of setting subclock operation → main clock operation
<1> MCK bit ← 0: Main clock starts oscillating
<2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
<3> CK3 bit ← 0: Use of a bit manipulation instruction is recommended. Do not change the CK2
to CK0 bits.
<4> Main clock operation: It takes the following time after the CK3 bit is set until main clock operation is
started.
Max.: 1/f
XT (1/subclock frequency)
Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0
or read the CLS bit to check if main clock operation has started.
Caution Enable operation of the on-chip peripheral functions operating with the main clock only after
the oscillation of the main clock stabilizes. If their operations are enabled before the lapse
of the oscillation stabilization time, a malfunction may occur.
[Description example]
_DMA_DISABLE:
clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3
<1> _START_MAIN_OSC :
st.b r0, PRCMD[r0] -- Release of protection of special registers
clr1 6, PCC[r0] -- Main clock starts oscillating.
<2> movea 0x55, r0, r11 -- Wait for oscillation stabilization time.
_WAIT_OST :
nop
nop
nop
addi -1, r11, r11
cmp r0, r11
bne _WAIT_OST
<3> st.b r0, PRCMD[r0]
clr1 3, PCC[r0] -- CK3 ← 0
<4> _CHECK_CLS :
tst1 4, PCC[r0] -- Wait until main clock operation starts.
bnz _CHECK_CLS
_DMA_ENABLE:
setl 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3
Remark The description above is simply an example. Note that in <4> above, the CLS bit is read in a
closed loop.