Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 179 of 870
Sep 30, 2010
FRC
Used
Not used
FRC
0
1
Use of subclock on-chip feedback resistor
PCC MCK MFRC CLS
Note
CK3 CK2 CK1 CK0
Oscillation enabled
Oscillation stopped
MCK
0
1
Main clock oscillator control
Used
Not used
MFRC
0
1
Use of main clock on-chip feedback resistor
After reset: 03H R/W Address: FFFFF828H
Main clock operation
Subclock operation
CLS
Note
0
1
Status of CPU clock (f
CPU )
Even if the MCK bit is set (1) while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions
operating with the main clock.
When the main clock is stopped and the device is operating with the subclock,
clear (0) the MCK bit and secure the oscillation stabilization time by software
before switching the CPU clock to the main clock or operating the on-chip
peripheral functions.
•
•
•
< >
< > < >
f XX
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /32
Setting prohibited
f
XT
CK2
0
0
0
0
1
1
1
×
Clock selection (f CLK /f CPU )CK1
0
0
1
1
0
0
1
×
CK0
0
1
0
1
0
1
×
×
CK3
0
0
0
0
0
0
0
1
Note The CLS bit is a read-only bit.
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
output.
2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Remark ×: don’t care