Datasheet

V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 176 of 870
Sep 30, 2010
6.2 Configuration
Figure 6-1. Clock Generator
Selector
Selector
Note
FRC bit
MFRC
bit
MCK
bit
CK2 to CK0
bits
SELPLL bit
PLLON
bit
CLS, CK3
bits
STOP mode
Subclock
oscillator
Port CM
Prescaler 1
Prescaler 2
IDLE
control
HALT
control
HALT
mode
CPU clock
Watch timer clock
Timer M clock
Watch timer clock,
watchdog timer 2 clock
Peripheral clock,
watchdog timer 2 clock
Watchdog timer 2 clock,
timer M clock
Internal
system clock
Prescaler 3
Main clock
oscillator
Main clock
oscillator
stop control
RSTOP bit
Internal
oscillator
1/8 divider
XT1
XT2
CLKOUT
X1
X2
IDLE mode
PLL
f
XX /32
f
XX /16
f
XX /8
f
XX /4
f
XX /2
f
XX
f CPU
f CLK
f XX to f XX /1,024
f
BRG = f X /2 to f X /2
12
f XT
f XT
f XX
f X
f R
f R /8
IDLE
control
Selector
Selector
Note The internal oscillation clock is selected when watchdog timer 2 overflows during the oscillation
stabilization time.
Remark f
X: Main clock oscillation frequency
f
XX: Main clock frequency
f
CLK: Internal system clock frequency
f
XT: Subclock frequency
fCPU: CPU clock frequency
f
BRG: Watch timer clock frequency
f
R: Internal oscillation clock frequency