Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 174 of 870
Sep 30, 2010
Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write)
CLKOUT
T1 T2
A1
D1 D2
Undefined
A2
Undefined
11 1110
D3
A3
T1 T2 THTI
Note
TI
Note
TH TH TH T1 T2
HLDRQ
HLDAK
A21 to A0
AD7 to AD0
WR1, WR0
11 10 11 10 11
Note This idle state (TI) does not depend on the BCC register settings.
Remark The broken lines indicate high impedance.
Figure 5-14. Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access)
TASW T1 TAHW T2
CLKOUT
ASTB
A21 to A0
WAIT
AD15 to AD0
RD
D1
A1
T1 T2
CLKOUT
ASTB
A21 to A0
WAIT
AD15 to AD0
RD
D1
A1
Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded.
2. TAHW (address hold wait): Image of low-level width of T1 state expanded.
3. The broken lines indicate high impedance.