Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 173 of 870
Sep 30, 2010
Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1
11 00 00 001111 11 11
A2 A3
T2 T1 TW TW T2 T1 T2
D3D2
Programmable
wait
External
wait
D1
CLKOUT
A21 to A0
WAIT
AD15 to AD0
WR1, WR0
WR1, WR0
01 10
8-bit access
AD15 to AD8
AD7 to AD0
Odd address
Active
Undefined
Even address
Undefined
Active
Remark The broken lines indicate high impedance.
Figure 5-12. Separate Bus Write Timing (Bus Size: 8 Bits)
T1
A1 A2 A3
T2 T1 TW TW T2 T1 T2
D3D2
Programmable
wait
External
wait
D1
CLKOUT
A21 to A0
WAIT
AD7 to AD0
WR1, WR0
11 10 10 1011 11 11 11
Remark The broken lines indicate high impedance.