Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 172 of 870
Sep 30, 2010
Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1 A2 A3
T2 T1 TW TW T2 T2TI T1
D3D2
Programmable
wait
External
wait
Idle state
D1
CLKOUT
A21 to A0
WAIT
AD15 to AD0
RD
8-bit access
AD15 to AD8
AD7 to AD0
Odd address
Active
Hi-Z
Even address
Hi-Z
Active
Remark The broken lines indicate high impedance.
Figure 5-10. Separate Bus Read Timing (Bus Size: 8 Bits)
T1
A1 A2 A3
T2 T1 TW TW T2 T2TI T1
D3D2
Programmable
wait
External
wait
Idle state
D1
CLKOUT
A21 to A0
WAIT
AD7 to AD0
RD
Remark The broken lines indicate high impedance.