Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 171 of 870
Sep 30, 2010
Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1
Undefined
A1
A2
T2 T3 TI
Note
TH TH TH TH TI
Note
T1 T2 T3
D1
CLKOUT
HLDRQ
HLDAK
A21 to A16
ASTB
AD15 to AD0
RD
Undefined Undefined
Undefined
A2 D2
Note This idle state (TI) does not depend on the BCC register settings.
Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode.
2. The broken lines indicate high impedance.