Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 170 of 870
Sep 30, 2010
Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)
A1
11 00 11 11 00 11
A2
A3
D1
D2
A3A2
A1
T2 T3 T1T1 T2 TW TW T3 T1
Programmable
wait
External
wait
CLKOUT
A21 to A16
ASTB
WAIT
AD15 to AD0
WR1, WR0
WR1, WR0
01 10
8-bit access
AD15 to AD8
AD7 to AD0
Odd address
Active
Undefined
Even address
Undefined
Active
Figure 5-7. Multiplexed Bus Write Timing (Bus Size: 8 Bits)
A1
11 10 11 11 10 11
A2
A3
D1
D2
A3A2
A1
T2 T3 T1T1 T2 TW TW T3 T1
Programmable
wait
External
wait
CLKOUT
A21 to A16,
AD15 to AD8
ASTB
WAIT
AD7 to AD0
WR1, WR0