Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 169 of 870
Sep 30, 2010
5.10 Bus Timing
Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)
A1 A2
A3
D1
D2
A3A2
A1
T1 T2 T3 T1 T2 TW TW T3 TI T1
Programmable
wait
External
wait
Idle state
CLKOUT
A21 to A16
ASTB
WAIT
AD15 to AD0
RD
8-bit access
AD15 to AD8
AD7 to AD0
Odd address
Active
Hi-Z
Even address
Hi-Z
Active
Remark The broken lines indicate high impedance.
Figure 5-5. Multiplexed Bus Read Timing (Bus Size: 8 Bits)
A1 A2
A3
D1
D2
A3A2
A1
T1 T2 T3 T1 T2 TW TW T3 TI T1
Programmable
wait
External
wait
Idle state
CLKOUT
A21 to A16,
AD15 to AD8
ASTB
WAIT
AD7 to AD0
RD
Remark The broken lines indicate high impedance.