Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 166 of 870
Sep 30, 2010
5.8 Bus Hold Function
5.8.1 Functional outline
The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the
external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the bus
mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again.
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until an on-
chip peripheral I/O register or the external memory is accessed.
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the
configuration of multi-processor type systems in which two or more bus masters exist.
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or
a bit manipulation instruction.
Status Data Bus
Width
Access Type Timing at Which Bus Hold Request
Is Not Acknowledged
Word access to even address Between first and second access
Between first and second access Word access to odd address
Between second and third access
16 bits
Halfword access to odd address Between first and second access
Between first and second access
Between second and third access
Word access
Between third and fourth access
CPU bus lock
8 bits
Halfword access Between first and second access
Read-modify-write access of bit
manipulation instruction
− −
Between read access and write
access