Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 165 of 870
Sep 30, 2010
5.7 Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle
that is executed for each space selected as the memory block in the multiplex address/data bus mode. In the separate bus
mode, one idle state (TI) can be inserted after the T2 state. By inserting an idle state, the data output float delay time of
the memory can be secured during read access (an idle state cannot be inserted during write access).
Whether the idle state is to be inserted can be programmed by using the BCC register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
The BCC register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state
insertion.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the BCC register are complete.
After reset: AAAAH R/W Address: FFFFF48AH
1
BC31
BCn1
0
1
Not inserted
Inserted
BCC 0
0
1
BC21
0
0
1
BC11
0
0
1
BC01
0
0
8
910
11
1213
Specifies insertion of idle state (n = 0 to 3)
1415
1234567 0
Memory block 0
Memory block 3
Memory block 2 Memory block 1
Caution Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to “0”.