Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 164 of 870
Sep 30, 2010
5.6.4 Programmable address wait function
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address
wait insertion is set for each memory block area (memory blocks 0 to 3).
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
address hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. Address setup wait and address hold wait cycles are not inserted when the internal ROM area,
internal RAM area, and on-chip peripheral I/O areas are accessed.
2. Write to the AWC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the AWC register are complete.
3. When the V850ES/JG3 is operated at f
XX > 20 MHz, be sure to insert the address hold wait and
the address setup wait.
After reset: FFFFH R/W Address: FFFFF488H
1
AHW3
AWC 1
ASW3
1
AHW2
1
ASW2
1
AHW1
1
ASW1
1
AHW0
1
ASW0
8
910
11
12131415
1234567 0
ASWn
0
1
Not inserted
Inserted
Setting prohibited
Inserted
Specifies insertion of address setup wait (n = 0 to 3)
Memory block 0
Memory block 3
Memory block 2 Memory block 1
fXX ≤ 20 MHz fXX > 20 MHz
AHWn
0
1
Not inserted
Inserted
Setting prohibited
Inserted
Specifies insertion of address hold wait (n = 0 to 3)
fXX ≤ 20 MHz fXX > 20 MHz
Caution Be sure to set bits 15 to 8 to “1”.