Datasheet
V850ES/JG3 CHAPTER 1 INTRODUCTION
R01UH0015EJ0300 Rev.3.00 Page 2 of 870
Sep 30, 2010
Table 1-1. V850ES/JG3 Product List
Part Number
μ
PD70F3739
μ
PD70F3740
μ
PD70F3741
μ
PD70F3742
Flash memory 384 KB 512 KB 768 KB 1024 KB
Internal
memory
RAM 32 KB 40 KB 60 KB 60 KB
Logical space 64 MB
Memory
space
External memory area 16 MB
External bus interface
Address bus: 22 bits
Data bus: 8/16 bits
Multiplex bus mode/separate bus mode
General-purpose register 32 bits × 32 registers
Main clock (oscillation frequency)
Ceramic/crystal
(in PLL mode: f
X = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 to 4 MHz (multiplied by 8),
in clock through mode: f
X = 2.5 to 10 MHz)
Subclock (oscillation frequency) Crystal (fXT = 32.768 kHz)
Internal oscillator fR = 220 kHz (TYP.)
Minimum instruction execution time 31.25 ns (main clock (fXX) = 32 MHz)
DSP function
32 × 32 = 64: 125 to 156.25 ns (at 32 MHz)
32 × 32 + 32 = 32: 187.5 ns (at 32 MHz)
16 × 16 = 32: 31.25 to 62.5 ns (at 32 MHz)
16 × 16 + 32 = 32: 93.75 ns (at 32 MHz)
I/O port I/O: 84 (5 V tolerant/N-ch open-drain output selectable: 40)
Timer
16-bit timer/event counter P: 6 channels
16-bit timer/event counter Q: 1 channel
16-bit interval timer M: 1 channel
Watch timer: 1 channel
Watchdog timer : 1 channel
Real-time output port 6 bits × 1 channel
A/D converter 10-bit resolution × 12 channels
D/A converter 8-bit resolution × 2 channels
Serial interface
UART/CSI: 1 channel
UART/I
2
C bus: 2 channels
CSI: 3 channels
CSI/I
2
C bus: 1 channel
DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
Interrupt source External: 9 (9)
Note
, internal: 48
Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
DCU Provided (RUN/break)
Operating power supply voltage 2.85 to 3.6 V
Operating ambient temperature −40 to +85°C
Package 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Note The figure in parentheses indicates the number of external interrupts that can release the STOP mode.