Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 162 of 870
Sep 30, 2010
5.6.2 External wait function
To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be
inserted in the bus cycle by using the external wait pin (WAIT).
When the PCM0 pin is set to alternate function, the external wait function is enabled.
Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the
external wait function, in the same manner as the programmable wait function.
The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and
TW states of the bus cycle in the multiplexed bus mode. In the separate bus mode, it is sampled at the rising edge of the
clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied,
a wait state is inserted in the next state, or not inserted at all.