Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 156 of 870
Sep 30, 2010
(3) Halfword access (16 bits)
(a) With 16-bit data bus width
<1> Access to even address (2n) <2> Access to odd address (2n + 1)
7
0
7
0
15
8
2n
Address
15
8
2n + 1
Halfword data External data
bus
First access Second access
7
0
7
0
15
8
15
8
7
0
7
0
15
8
15
8
2n + 2
Halfword data External data
bus
2n
Address
Halfword data External data
bus
Address
2n + 1
(b) 8-bit data bus width
<1> Access to even address (2n) <2> Access to odd address (2n + 1)
First access Second access
7
0
7
0
15
8
Address
7
0
7
0
15
8
2n + 1
Address
2n
Halfword data External data
bus
Halfword data External data
bus
First access Second access
7
0
7
0
15
8
7
0
7
0
15
8
2n + 2
2n + 1
Address
Address
Halfword data External data
bus
Halfword data External data
bus