Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 153 of 870
Sep 30, 2010
5.5 Bus Access
5.5.1 Number of clocks for access
The following table shows the number of basic clocks required for accessing each resource.
Area (Bus Width)
Bus Cycle Type
Internal ROM (32 Bits) Internal RAM (32 Bits) External Memory (16 Bits)
Instruction fetch (normal access) 1 1
Note 1
3 + n
Note 2
Instruction fetch (branch) 2 2
Note 1
3 + n
Note 2
Operand data access 3 1 3 + n
Note 2
Notes 1. Increases by 1 if a conflict with a data access occurs.
2. 2 + n clocks (n: Number of wait states) when the separate bus mode is selected.
Remark Unit: Clocks/access
5.5.2 Bus size setting function
Each external memory area selected by memory block can be set by using the BSC register. However, the bus size
can be set to 8 bits and 16 bits only.
The external memory area of the V850ES/JG3 is selected by memory blocks 0 to 3.
(1) Bus size configuration register (BSC)
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access
an external memory area until the initial settings of the BSC register are complete.
After reset: 5555H R/W Address: FFFFF066H
0
0
BSn0
0
1
8 bits
16 bits
BSC 1
BS30
0
0
1
BS20
0
0
1
BS10
0
0
1
BS00
8
910
11
1213
Data bus width of CSn space (n = 0 to 3)
1415
1234567 0
Memory block 0
Memory block 3
Memory block 2 Memory block 1
Caution Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.