Datasheet

V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 150 of 870
Sep 30, 2010
5.2 Bus Control Pins
The pins used to connect an external device are listed in the table below.
Table 5-1. Bus Control Pins (Multiplexed Bus)
Bus Control Pin Alternate-Function Pin I/O Function
AD0 to AD15 PDL0 to PDL15 I/O Address/data bus
A16 to A21 PDH0 to PDH5 Output Address bus
WAIT PCM0 Input External wait control
CLKOUT PCM1 Output Internal system clock
WR0, WR1 PCT0, PCT1 Output Write strobe signal
RD PCT4 Output Read strobe signal
ASTB PCT6 Output Address strobe signal
HLDRQ PCM3 Input
HLDAK PCM2 Output
Bus hold control
Table 5-2. External Control Pins (Separate Bus)
Bus Control Pin Alternate-Function Pin I/O Function
AD0 to AD15 PDL0 to PDL15 I/O Data bus
A0 to A15 P90 to P915 Output Address bus
A16 to A21 PDH0 to PDH5 Output Address bus
WAIT PCM0 Input External wait control
CLKOUT PCM1 Output Internal system clock
WR0, WR1 PCT0, PCT1 Output Write strobe signal
RD PCT4 Output Read strobe signal
HLDRQ PCM3 Input
HLDAK PCM2 Output
Bus hold control
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Table 5-3. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Separate Bus Mode Multiplexed Bus Mode
Address bus (A21 to A0) Undefined Address bus (A21 to A16) Undefined
Data bus (AD15 to AD0) Hi-Z Address/data bus (AD15 to AD0) Undefined
Control signal Inactive Control signal Inactive
Caution When a write access is performed to the internal ROM area, address, data, and control signals are
activated in the same way as access to the external memory area.
5.2.2 Pin status in each operation mode
For the pin status of the V850ES/JG3 in each operation mode, see 2.2 Pin States.