Datasheet

V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 148 of 870
Sep 30, 2010
4.6.3 Cautions on on-chip debug pins
The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins.
After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a
high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can
be used.
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P05/INTP2/DRST pin to low level from when reset by the RESET pin is released until the above
action is taken.
If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock).
Handle the P05 pin with the utmost care.
Caution After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the
P05/INTP2/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM register
holds the current value.
4.6.4 Cautions on P05/INTP2/DRST pin
The P05/INTP2/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a reset by the RESET pin, a pull-down
resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).
4.6.5 Cautions on P53 pin when power is turned on
When the power is turned on, the following pin may output an undefined level temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
4.6.6 Hysteresis characteristics
In port mode, the following port pins do not have hysteresis characteristics.
P02 to P06
P31 to P35, P38, P39
P40 to P42
P50 to P55
P90 to P97, P99, P910, P912 to P915