Datasheet

V850ES/JG3 CHAPTER 4 PORT FUNCTIONS

R01UH0015EJ0300 Rev.3.00 Page 105 of 870

Sep 30, 2010

(3) Port DL mode control register (PMCDL)

I/O port

ADn I/O (address/data bus I/O)

PMCDLn

Specification of PDLn pin operation mode (n = 0 to 15)

PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0

After reset: 0000H R/W Address: PMCDL FFFFF044H,

PMCDLL FFFFF044H, PMCDLH FFFFF045H

PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8

89101112131415

PMCDL (PMCDLH)

(PMCDLL)

Caution When the SMSEL bit of the EXIMC register = 1 (separate mode) and the BS30 to BS00

bits of the BSC register = 0 (8-bit bus width), do not specify the AD8 to AD15 pins.

Remarks 1. The PMCDL register can be read or written in 16-bit units.

However, when using the higher 8 bits of the PMCDL register as the PMCDLH register

and the lower 8 bits as the PMCDLL register, PMCDL can be read or written in 8-bit or 1-

bit units.

2. To read/write bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify them as bits

0 to 7 of the PMCDLH register.