Datasheet

V850ES/JG3 CHAPTER 4 PORT FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 86 of 870
Sep 30, 2010
PFCE52 PFC52 Specification of P52 pin alternate function
0 0 Setting prohibited
0 1 TIQ03 input/KR2
Note
input
1 0 TOQ03 input
1 1 RTP02 output
PFCE51 PFC51 Specification of P51 pin alternate function
0 0 Setting prohibited
0 1 TIQ02 input/KR1
Note
input
1 0 TOQ02 output
1 1 RTP01 output
PFCE50 PFC50 Specification of P50 pin alternate function
0 0 Setting prohibited
0 1 TIQ01 input/KR0
Note
input
1 0 TOQ01 output
1 1 RTP00 output
Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, disable
KRn pin key return detection, which is the alternate function. (Clear the KRM.KRMn bit to 0.) Also, when
using the pin as the KRn pin, disable TIQ0m pin edge detection, which is the alternate function (n = 0 to 3,
m = 0 to 3).
Pin Name Use as TIQ0m Pin Use as KRn Pin
KR0/TIQ01 KRM.KRM0 bit = 0 TQ0IOC1. TQ0TIG2, TQ0IOC1. TQ0TIG3 bits = 0
KR1/TIQ02 KRM.KRM1 bit = 0 TQ0IOC1.TQ0TIG4, TQ0IOC1.TQ0TIG5 bits = 0
KR2/TIQ03 KRM.KRM2 bit = 0 TQ0IOC1.TQ0TIG6, TQ0IOC1.TQ0TIG7 bits = 0
KR3/TIQ00 KRM.KRM3 bit = 0
TQ0IOC1.TQ0TIG0, TQ0IOC1.TQ0TIG1 bits = 0
TQ0IOC2.TQ0EES0, TQ0IOC2.TQ0EES1 bits = 0
TQ0IOC2.TQ0ETS0, TQ0IOC2.TQ0ETS1 bits = 0
(7) Port 5 function register (PF5)
0
Normal output (CMOS output)
N-ch open-drain output
PF5n
0
1
Control of normal output or N-ch open-drain output (n = 0 to 5)
PF5 0 PF55 PF54 PF53 PF52 PF51 PF50
After reset: 00H R/W Address: FFFFFC6AH
Caution When an output pin is pulled up at EV
DD or higher, be sure to set the PF5n bit to 1.