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Rev.3.00 Sep 2010

User’s Manual

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

V850ES/JG3

User’s Manual: Hardware

RENESAS MCU

V850ES/JG3 Microcontrollers

μ PD70F3739

μPD70F3740

μPD70F3741

μPD70F3742

Summary of content (889 pages)

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User’s Manual 32 V850ES/JG3 User’s Manual: Hardware RENESAS MCU V850ES/JG3 Microcontrollers μPD70F3739 μPD70F3740 μPD70F3741 μPD70F3742 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
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How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3 and design application systems using the V850ES/JG3. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG3 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User’s Manual).
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Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the Note: Footnote for item marked with Note in the text bottom Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JG3 Hardware User’s Manual This manual Documents related to development tools Document Name Document No.
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Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America. EEPROM is a trademark of Renesas Electronics Corporation.
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CONTENTS CHAPTER 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER 2.1 2.2 2.3 2.4 1 INTRODUCTION....................................................................................................................1 General .......................................................................................................................................1 Features......................................................................................................................................3 Application Fields.....
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4.4 4.5 4.3.10 Port DH ....................................................................................................................................101 4.3.11 Port DL.....................................................................................................................................103 Block Diagrams..................................................................................................................... 106 Port Register Settings When Alternate Function Is Used ......
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7.6 7.7 CHAPTER 8.1 8.2 8.3 8.4 8.5 8.6 CHAPTER 9.1 9.2 9.3 9.4 CHAPTER 10.1 10.2 10.3 10.4 CHAPTER 11.1 11.2 11.3 11.4 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)...............................................234 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ..............................................................241 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) ....................................................250 7.5.
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12.3 12.4 12.5 12.6 CHAPTER 13.1 13.2 13.3 13.4 13.5 13.6 13.7 CHAPTER 14.1 14.2 14.3 14.4 Registers ............................................................................................................................... 402 Operation............................................................................................................................... 404 Usage ..................................................................................................................................
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CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB).................................................... 484 16.1 Mode Switching of CSIB and Other Serial Interfaces ....................................................... 484 16.2 16.3 16.4 16.5 16.6 16.1.1 CSIB4 and UARTA0 mode switching.......................................................................................484 16.1.2 CSIB0 and I2C01 mode switching ...........................................................................................
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17.8 17.9 17.10 17.11 17.12 17.13 17.14 17.7.4 Operation without communication............................................................................................577 17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................577 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ...................579 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control.......................
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19.5 19.6 19.7 19.8 19.9 19.4.1 Operation .................................................................................................................................657 19.4.2 Restore ....................................................................................................................................658 19.4.3 EP flag .....................................................................................................................................659 Exception Trap...........
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22.3.5 Reset function operation flow...................................................................................................701 CHAPTER 23.1 23.2 23.3 23.4 23 CLOCK MONITOR ........................................................................................................ 702 Functions............................................................................................................................... 702 Configuration .............................................................
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28.2 28.3 28.1.1 Connection circuit example ......................................................................................................747 28.1.2 Interface signals.......................................................................................................................747 28.1.3 Maskable functions ..................................................................................................................749 28.1.4 Register ..............................................
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R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 V850ES/JG3 RENESAS MCU CHAPTER 1 INTRODUCTION The V850ES/JG3 is one of the products in the Renesas Electronics V850 single-chip microcontrollers designed for lowpower operation for real-time control applications. 1.1 General The V850ES/JG3 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
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V850ES/JG3 CHAPTER 1 INTRODUCTION Table 1-1.
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V850ES/JG3 1.2 CHAPTER 1 INTRODUCTION Features Minimum instruction execution time: 31.
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V850ES/JG3 1.3 CHAPTER 1 INTRODUCTION Application Fields Home audio, printers, digital home electronics, other consumer devices 1.
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V850ES/JG3 1.
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V850ES/JG3 CHAPTER 1 INTRODUCTION Pin names A0 to A21: Address bus PDH0 to PDH5: Port DH AD0 to AD15: Address/data bus PDL0 to PDL15: Port DL ADTRG: A/D trigger input RD: Read strobe ANI0 to ANI11: Analog input REGC: Regulator control ANO0, ANO1: Analog output RESET: Reset ASCKA0: Asynchronous serial clock RTP00 to RTP05: Real-time output port ASTB: Address strobe RXDA0 to RXDA2: Receive data AVREF0, AVREF1: Analog reference voltage SCKB0 to SCKB4: Serial clock AVSS: Analo
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V850ES/JG3 Function Block Configuration 1.6.
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V850ES/JG3 1.6.2 CHAPTER 1 INTRODUCTION Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
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V850ES/JG3 CHAPTER 1 INTRODUCTION (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs.
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V850ES/JG3 CHAPTER 1 INTRODUCTION (19) Ports The general-purpose port functions and control pin functions are listed below.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins in the V850ES/JG3 are described below. There are three types of pin I/O buffer power supplies: AVREF0, AVREF1, and EVDD. The relationship between these power supplies and the pins is described below. Table 2-1.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name P40 Pin No. 22 I/O I/O Function Port 4 Alternate Function SIB0/SDA01 3-bit I/O port P41 Input/output can be specified in 1-bit units. 23 SOB0/SCL01 N-ch open-drain output can be specified in 1-bit units. P42 24 P50 37 P51 P52 5 V tolerant. I/O Port 5 6-bit I/O port 38 Input/output can be specified in 1-bit units. 39 N-ch open-drain output can be specified in 1-bit units. 5 V tolerant.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PCM0 PCM1 Pin No. 61 63 PCM3 64 PCT0 65 67 PCT6 68 PDH0 87 Function Port CM 4-bit I/O port Input/output can be specified in 1-bit units. Alternate Function WAIT CLKOUT HLDAK HLDRQ I/O Port CT 4-bit I/O port 66 PCT4 PDH1 I/O 62 PCM2 PCT1 I/O Input/output can be specified in 1-bit units. WR0 WR1 RD ASTB I/O Port DH 6-bit I/O port 88 Input/output can be specified in 1-bit units.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/5) Pin Name A0 A1 Pin No. I/O 43 Output 44 Function Alternate Function Address bus for external memory P90/KR6/TXDA1/SDA02 (when using separate bus) P91/KR7/RXDA1/SCL02 N-ch open-drain output selectable.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (2/5) Pin Name Pin No. I/O Function Alternate Function ADTRG 18 Input A/D converter external trigger input. 5 V tolerant. P03/INTP0 ANI0 100 Input Analog voltage input for A/D converter P70 ANI1 99 P71 ANI2 98 P72 ANI3 97 P73 ANI4 96 P74 ANI5 95 P75 ANI6 94 P76 ANI7 93 P77 ANI8 92 P78 ANI9 91 P79 ANI10 90 P710 ANI11 89 P711 ANO0 3 ANO1 4 ASCKA0 27 Input UARTA0 baud rate clock input. 5 V tolerant.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (3/5) Pin Name INTP0 Pin No. 18 INTP1 I/O Input 19 Function Alternate Function External interrupt request input (maskable, analog noise P03/ADTRG elimination). P04 Analog noise elimination or digital noise elimination INTP2 20 INTP3 21 INTP4 56 P913/A13 INTP5 57 P914/A14/TIP51/TOP51 INTP6 58 P915/A15/TIP50/TOP50 INTP7 26 P31/RXDA0/SIB4 selectable for INTP3 pin. 5 V tolerant.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (4/5) Pin Name SCL00 SCL01 SCL02 Pin No. 36 I/O I/O 23 35 SDA01 22 SDA02 43 SIB0 22 SIB1 50 SIB2 40 Alternate Function 2 Serial clock I/O (I C00 to I C02) P39/RXDA2 N-ch open-drain output selectable. P41/SOB0 5 V tolerant. 44 SDA00 Function 2 I/O P91/A1/KR7/RXDA1 2 2 Serial transmit/receive data I/O (I C00 to I C02) P38/TXDA2 N-ch open-drain output selectable. P40/SIB0 5 V tolerant.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (5/5) Pin Name TOP00 Pin No. I/O 27 Output Function Alternate Function Timer output (TMP0) P32/ASCKA0/SCKB4/TIP00 P33/TIP01 TOP01 28 N-ch open-drain output selectable. 5 V tolerant. TOP10 29 Timer output (TMP1) P34/TIP10 TOP11 30 N-ch open-drain output selectable. 5 V tolerant. P35/TIP11 TOP20 50 Timer output (TMP2) P97/A7/SIB1/TIP20 TOP21 49 N-ch open-drain output selectable. 5 V tolerant.
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V850ES/JG3 2.2 CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various modes are described below. Table 2-2.
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V850ES/JG3 2.3 CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins (1/3) Pin Alternate Function Pin No. I/O Circuit Type 10-D P02 NMI 17 P03 INTP0/ADTRG 18 P04 INTP1 19 P05 INTP2/DRST 20 Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 10-N Input: Independently connect to EVSS via a resistor. Fixing to VDD level is prohibited. Output: Leave open.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (2/3) Pin P70 to P711 Alternate Function ANI0 to ANI11 Pin No. I/O Circuit Type 100-89 11-G Recommended Connection Input: Independently connect to AVREF0 or AVSS via a resistor. Output: Leave open. P90 A0/KR6/TXDA1/SDA02 43 P91 A1/KR7/RXDA1/SCL02 44 10-D via a resistor.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS (3/3) Pin AVREF0 Alternate Function Pin No. I/O Circuit Type − 1 − Recommended Connection Directly connect to VDD and always supply power. AVREF1 − 5 − Directly connect to VDD and always supply power. AVSS − 2 − Directly connect to VSS and always supply power. EVDD − 34, 70 − Directly connect to VDD and always supply power. EVSS − 33, 69 − Directly connect to VSS and always supply power.
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V850ES/JG3 CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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V850ES/JG3 2.4 CHAPTER 2 PIN FUNCTIONS Cautions When the power is turned on, the following pin may output an undefined level temporarily, even during reset. • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JG3 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 31.25 ns (at 32 MHz operation) 30.5 μs (with subclock (fXT) = 32.
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V850ES/JG3 3.2 CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JG3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual.
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V850ES/JG3 3.2.1 CHAPTER 3 CPU FUNCTION Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used.
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V850ES/JG3 3.2.2 CHAPTER 3 CPU FUNCTION System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW. The address of the instruction next to the one of the instruction under execution, except some instructions, is saved to FEPC when an NMI occurs. The current contents of the PSW are saved to FEPSW.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs.
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V850ES/JG3 3.3 CHAPTER 3 CPU FUNCTION Operation Modes The V850ES/JG3 has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started. (2) Flash memory programming mode In this mode, the internal flash memory can be programmed by using a flash programmer.
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V850ES/JG3 3.4 3.4.1 CHAPTER 3 CPU FUNCTION Address Space CPU address space For instruction addressing, up to a combined total of 16 MB of an external memory area and an internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space.
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V850ES/JG3 3.4.2 CHAPTER 3 CPU FUNCTION Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses.
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V850ES/JG3 3.4.3 CHAPTER 3 CPU FUNCTION Memory map The areas shown below are reserved in the V850ES/JG3. Figure 3-2.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 03FFFFFFH 03FFF000H 03FFEFFFH Use prohibited (program fetch prohibited area) Internal RAM area (60 KB) 03FF0000H 03FEFFFFH Use prohibited (program fetch prohibited area) 01000000H 00FFFFFFH External memory area (14 MB) 00200000H 001FFFFFH 00100000H 000FFFFFH 00000000H R01UH0015EJ0300 Rev.3.
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V850ES/JG3 3.4.4 CHAPTER 3 CPU FUNCTION Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (384 KB) 384 KB are allocated to addresses 00000000H to 0005FFFFH in the μPD70F3739. Accessing addresses 00060000H to 000FFFFFH is prohibited. Figure 3-4. Internal ROM Area (384 KB) 000FFFFFH Access-prohibited area 00060000H 0005FFFFH Internal ROM (384 KB) 00000000H (b) Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the μPD70F3740.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (c) Internal ROM (768 KB) 768 KB are allocated to addresses 00000000H to 000BFFFFH in the μPD70F3741. Accessing addresses 000C0000H to 000FFFFFH is prohibited. Figure 3-6. Internal ROM Area (768 KB) 000FFFFFH 000C0000H 000BFFFFH Access-prohibited area Internal ROM (768 KB) 00000000H (d) Internal ROM (1024 KB) 1024 KB are allocated to addresses 00000000H to 000FFFFFH in the μPD70F3742. Figure 3-7.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. (a) Internal RAM (32 KB) 32 KB are allocated to addresses 03FF7000H to 03FFEFFFH in the μPD70F3739. Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. Figure 3-8.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (c) Internal RAM (60 KB) 60 KB are allocated to addresses 03FF0000H to 03FFEFFFH in the μPD70F3741 and 70F3742. Figure 3-10. Internal RAM Area (60 KB) Physical address space Logical address space 03FFEFFFH FFFFEFFFH Internal RAM 03FF0000H R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-11. On-Chip Peripheral I/O Area Physical address space Logical address space 03FFFFFFH FFFFFFFFH On-chip peripheral I/O area (4 KB) 03FFF000H FFFFF000H Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip peripheral I/O are mapped to the on-chip peripheral I/O area.
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V850ES/JG3 3.4.5 CHAPTER 3 CPU FUNCTION Recommended use of address space The architecture of the V850ES/JG3 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION Figure 3-12.
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V850ES/JG3 3.4.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (2/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 R/W 16 √ 0000H √ 0000H FFFFF0D2H DMA addressing control register 1 DADC1 FFFFF0D4H DMA addressing control register 2 DADC2 FFFFF0D6H DMA addressing control register 3 DADC3 FFFFF0E0H DMA channel control register 0 DCHC0 √ √ 00H FFFFF0E2H DMA channel control register 1 DCHC1 √ √ 00H FFFFF0E4H DMA channel control register 2 DCHC2 √ √ 00H FFFFF0E6H DMA
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (3/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 47H TP3CCIC1 √ √ 47H TP4OVIC √ √ 47H Interrupt control register TP4CCIC0 √ √ 47H FFFFF148H Interrupt control register TP4CCIC1 √ √ 47H FFFFF14AH Interrupt control register TP5OVIC √ √ 47H FFFFF14CH Interrupt control register TP5CCIC0 √ √ 47H FFFFF14EH Interrupt control register TP5CCIC1 √ √ 47H FFFFF150H Interrupt control register TM0EQI
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (4/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF210H FFFFF211H FFFFF212H FFFFF213H FFFFF214H FFFFF215H FFFFF216H FFFFF217H FFFFF218H FFFFF219H FFFFF21AH FFFFF21BH FFFFF21CH FFFFF21DH FFFFF21EH FFFFF21FH FFFFF220H FFFFF221H FFFFF222H FFFFF223H FFFFF224H FFFFF225H FFFFF226H A/D conversion result register 0 ADA0CR0 A/D conversion result register 0H ADA0CR0H A/D conversion result register 1 ADA0CR1 A/D conversion result regi
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (5/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF406H 8 16 √ R/W Note Port 3 register P3 0000H FFFFF406H Port 3 register L P3L √ √ 00H FFFFF407H Port 3 register H P3H √ √ 00H FFFFF408H Port 4 register P4 √ √ 00H Note FFFFF40AH Port 5 register P5 √ √ 00H Note FFFFF40EH Port 7 register L P7L √ √ 00H Note FFFFF40FH Port 7 register H P7H √ √ 00H FFFFF412H Port 9 register P9 FFFFF412H
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (6/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF484H 8 16 √ 7777H AWC √ FFFFH BCC √ AAAAH Data wait control register 0 DWC0 FFFFF488H Address wait control register FFFFF48AH Bus cycle control register FFFFF540H TMQ0 control register 0 TQ0CTL0 √ √ 00H R/W FFFFF541H TMQ0 control register 1 TQ0CTL1 √ √ 00H FFFFF542H TMQ0 I/O control register 0 TQ0IOC0 √ √ 00H FFFFF543H TMQ0 I/O control register
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (7/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 00H TP3IOC1 √ √ 00H TP3IOC2 √ √ 00H TMP3 option register 0 TP3OPT0 √ √ 00H FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0 √ 0000H FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1 √ 0000H FFFFF5CAH TMP3 counter read buffer register TP3CNT R √ 0000H FFFFF5D0H TMP4 control register 0 TP4CTL0 R/W FFFFF5D1H TMP4 control register 1 TP4CTL1 √
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (8/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 00H DTFR2 √ √ 00H DTFR3 √ √ 00H PSMR √ √ 00H √ √ 0AH √ √ 00H FFFFF812H DMA trigger factor register 1 DTFR1 FFFFF814H DMA trigger factor register 2 FFFFF816H DMA trigger factor register 3 FFFFF820H Power save mode register R/W FFFFF822H Clock control register CKC FFFFF824H Lock register LOCKR FFFFF828H Processor clock control register PCC
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (9/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 √ √ 00H INTR0 √ √ 00H INTR3 √ √ 00H External interrupt rising edge specification register 9H INTR9H √ √ 00H FFFFFC60H Port 0 function register PF0 √ √ FFFFFC66H Port 3 function register PF3 FFFFFC66H Port 3 function register L PF3L √ √ 00H FFFFFC67H Port 3 function register H PF3H √ √ 00H FFFFFC13H External interrupt falling edge specification reg
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (10/10) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFFD36H CSIB3 transmit data register CB3TX 8 16 √ R/W 0000H CSIB3 transmit data register L CB3TXL √ 00H FFFFFD40H CSIB4 control register 0 CB4CTL0 √ √ 01H FFFFFD41H CSIB4 control register 1 CB4CTL1 √ √ 00H FFFFFD42H CSIB4 control register 2 CB4CTL2 √ 00H FFFFFD43H CSIB4 status register CB4STR √ 00H FFFFFD44H CSIB4 receive data register CB4RX CSIB4
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V850ES/JG3 3.4.7 CHAPTER 3 CPU FUNCTION Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JG3 has the following eight special registers.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4> Write the setting data to the special register (by using the following instructions).
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF802H < > SYS 0 0 0 PRERR 0 0 0 0 PRERR Detects protection error 0 Protection error did not occur 1 Protection error occurred The PRERR flag operates under the following conditions.
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V850ES/JG3 3.4.8 CHAPTER 3 CPU FUNCTION Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JG3. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred.
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V850ES/JG3 CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> • ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu • sld instruction: sld.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Features { I/O ports: 84 • 5 V tolerant/N-ch open-drain output selectable: 40 (ports 0, 3 to 5, 9) { Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JG3 features a total of 84 I/O ports consisting of ports 0, 1, 3 to 5, 7, 9, CM, CT, DH, and DL. The port configuration is shown below. Figure 4-1.
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V850ES/JG3 4.3 CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-2.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-2.
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V850ES/JG3 4.3.1 CHAPTER 4 PORT FUNCTIONS Port 0 Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-4. Port 0 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) After reset: FFH R/W PM0 PM06 1 Address: FFFFF420H PM05 PM0n PM04 PM03 PM02 1 1 0 0 I/O mode control (n = 2 to 6) 0 Output mode 1 Input mode (3) Port 0 mode control register (PMC0) After reset: 00H PMC0 0 R/W Address: FFFFF440H PMC06 PMC05 PMC06 PMC03 PMC02 Specification of P06 pin operation mode 0 I/O port 1 INTP3 input PMC05 Specification of P05 pin operation mode 0 I/O port 1 INTP2 input PMC04
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (4) Port 0 function control register (PFC0) After reset: 00H PFC0 0 R/W Address: FFFFF460H 0 0 PFC03 0 PFC03 0 0 0 Specification of P03 pin alternate function 0 INTP0 input 1 ADTRG input (5) Port 0 function register (PF0) After reset: 00H PF0 0 PF0n Caution R/W Address: FFFFFC60H PF06 PF05 PF04 PF03 PF02 0 0 Control of normal output or N-ch open-drain output (n = 2 to 6) 0 Normal output (CMOS output) 1 N-ch open drain output When a
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V850ES/JG3 4.3.2 CHAPTER 4 PORT FUNCTIONS Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Table 4-5. Port 1 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 4.3.3 CHAPTER 4 PORT FUNCTIONS Port 3 Port 3 is a 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-6. Port 3 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 0000H (output latch) P3 (P3H) (P3L) R/W Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P3n Output data control (in output mode) (n = 0 to 9) 0 Outputs 0. 1 Outputs 1. Remarks 1. The P3 register can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H R/W Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H 15 14 13 12 11 10 9 8 PMC3 (PMC3H) 0 0 0 0 0 0 PMC39 PMC38 (PMC3L) 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode 0 I/O port 1 RXDA2 input/SCL00 I/O PMC38 Specification of P38 pin operation mode 0 I/O port 1 TXDA2 output/SDA00 I/O PMC35 Specification of P35 pin operation
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 0000H R/W Address: PFC3 FFFFF466H, PFC3L FFFFF466H, PFC3H FFFFF467H 15 14 13 12 11 10 9 8 PFC3 (PFC3H) 0 0 0 0 0 0 PFC39 PFC38 (PFC3L) 0 0 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 Remarks 1. For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications. 2. The PFC3 register can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (6) Port 3 alternate function specifications PFC39 Specification of P39 pin alternate function 0 RXDA2 input 1 SCL00 input PFC38 Specification of P38 pin alternate function 0 TXDA2 output 1 SDA00 I/O PFC35 Specification of P35 pin alternate function 0 TIP11 input 1 TOP11 output PFC34 Specification of P34 pin alternate function 0 TIP10 input 1 TOP10 output PFC33 Specification of P33 pin alternate function 0 TIP01 input 1 TOP01 output PFCE32
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 0000H 14 13 12 11 10 9 8 0 0 0 0 0 0 PF39 PF38 PF37 PF36 PF35 PF34 PF33 PF32 PF31 PF30 PF3n Caution Address: PF3 FFFFFC66H, PF3L FFFFFC66H, PF3H FFFFFC67H 15 PF3 (PF3H) (PF3L) R/W Control of normal output or N-ch open-drain output (n = 0 to 9) 0 Normal output (CMOS output) 1 N-ch open-drain output When an output pin is pulled up at EVDD or higher, be sure to set the PF3n bit to 1.
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V850ES/JG3 4.3.4 CHAPTER 4 PORT FUNCTIONS Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-7. Port 4 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 R/W Address: FFFFF448H 0 0 PMC42 0 0 PMC42 PMC41 PMC40 Specification of P42 pin operation mode 0 I/O port 1 SCKB0 I/O PMC41 Specification of P41 pin operation mode 0 I/O port 1 SOB0 output/SCL01 I/O PMC40 Specification of P40 pin operation mode 0 I/O port 1 SIB0 input/SDA01 I/O (4) Port 4 function control register (PFC4) After reset: 00H PFC4 0 R/W Address: FFFFF468H 0
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (5) Port 4 function register (PF4) After reset: 00H PF4 0 PF4n Caution R/W 0 Address: FFFFFC68H 0 0 0 PF42 PF41 PF40 Control of normal output or N-ch open-drain output (n = 0 to 2) 0 Normal output (CMOS output) 1 N-ch open-drain output When an output pin is pulled up at EVDD or higher, be sure to set the PF4n bit to 1. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 4.3.5 CHAPTER 4 PORT FUNCTIONS Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-8. Port 5 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (2) Port 5 mode register (PM5) After reset: FFH PM5 1 R/W Address: FFFFF42AH 1 PM55 PM5n PM54 PM53 PM52 PM51 PM50 PMC51 PMC50 I/O mode control (n = 0 to 5) 0 Output mode 1 Input mode (3) Port 5 mode control register (PMC5) After reset: 00H PMC5 0 R/W 0 PMC55 Address: FFFFF44AH PMC55 PMC54 PMC53 PMC52 Specification of P55 pin operation mode 0 I/O port 1 SCKB2 I/O/KR5 input/RTP05 output PMC54 Specification of P54 pin operation mode
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) After reset: 00H PFC5 Remark R/W 0 0 Address: FFFFF46AH PFC55 PFC54 PFC53 PFC52 PFC51 For details of alternate function specification, see 4.3.5 (6) PFC50 Port 5 alternate function specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H PFCE5 Remark R/W 0 0 Address: FFFFF70AH PFCE55 PFCE54 PFCE53 PFCE52 PFCE51 For details of alternate function specification, see 4.3.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS PFCE52 PFC52 Specification of P52 pin alternate function 0 0 Setting prohibited 0 1 TIQ03 input/KR2 1 0 TOQ03 input 1 1 RTP02 output PFCE51 PFC51 0 0 Setting prohibited 0 1 TIQ02 input/KR1 1 0 TOQ02 output 1 1 RTP01 output PFCE50 PFC50 0 0 Setting prohibited 0 1 TIQ01 input/KR0 1 0 TOQ01 output 1 1 RTP00 output Note input Specification of P51 pin alternate function Note input Specification of P50 pin alternate function No
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V850ES/JG3 4.3.6 CHAPTER 4 PORT FUNCTIONS Port 7 Port 7 is a 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-9. Port 7 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (1) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) R/W Address: P7L FFFFF40EH, P7H FFFFF40FH P7H 0 0 0 0 P711 P710 P79 P78 P7L P77 P76 P75 P74 P73 P72 P71 P70 P7n Caution Output data control (in output mode) (n = 0 to 11) 0 Outputs 0 1 Outputs 1 Do not read/write the P7H and P7L registers during A/D conversion (see 13.6 (4) Alternate I/O).
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V850ES/JG3 4.3.7 CHAPTER 4 PORT FUNCTIONS Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-10. Port 9 Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) R/W Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 15 14 13 12 11 10 9 8 P9 (P9H) P915 P914 P913 P912 P911 P910 P99 P98 (P9L) P97 P96 P95 P94 P93 P92 P91 P90 P9n Output data control (in output mode) (n = 0 to 15) 0 Outputs 0 1 Outputs 1 Remarks 1. The P9 register can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/2) After reset: 0000H 15 PMC9 (PMC9H) (PMC9L) R/W 14 Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H 9 8 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 PMC97 PMC91 PMC90 PMC96 PMC915 13 12 PMC95 PMC94 11 PMC93 10 PMC92 Specification of P915 pin operation mode 0 I/O port 1 A15 output/INTP6 input/TIP50 input/TOP50 output PMC914 Specification of P914 pin operation mode 0 I/O port 1
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (2/2) PMC98 Specification of P98 pin operation mode 0 I/O port 1 A8 output/SOB1 output PMC97 Specification of P97 pin operation mode 0 I/O port 1 A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 Specification of P96 pin operation mode 0 I/O port 1 A6 output/TIP21 input/TOP21 output PMC95 Specification of P95 pin operation mode 0 I/O port 1 A5 output/TIP30 input/TOP30 output PMC94 Specification of P94 pin operation mode 0 I/O port 1 A4 out
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 or PFCE9 register to 0000H.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications PFCE915 PFC915 0 0 A15 output 0 1 INTP6 input 1 0 TIP50 input 1 1 TOP50 output PFCE914 PFC914 0 0 A14 output 0 1 INTP5 input 1 0 TIP51 input 1 1 TOP51 output PFC913 Specification of P915 pin alternate function Specification of P914 pin alternate function Specification of P913 pin alternate function 0 A13 output 1 INTP4 input PFC912 Specification of P912 pin alternate function 0 A12 outpu
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS PFCE96 PFC96 Specification of P96 pin alternate function 0 0 A6 output 0 1 Setting prohibited 1 0 TIP21 input 1 1 TOP21 output PFCE95 PFC95 0 0 A5 output 0 1 TIP30 input 1 0 TOP30 output 1 1 Setting prohibited PFCE94 PFC94 0 0 A4 output 0 1 TIP31 input 1 0 TOP31 output 1 1 Setting prohibited PFCE93 PFC93 0 0 A3 output 0 1 TIP40 input 1 0 TOP40 output 1 1 Setting prohibited PFCE92 PFC92 0 0 A2 output 0 1 TIP
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) After reset: 0000H PF9 (PF9H) (PF9L) Address: PF3 FFFFFC72H, PF9L FFFFFC72H, PF9H FFFFFC73H 15 14 13 12 11 10 9 8 PF915 PF914 PF913 PF912 PF911 PF910 PF99 PF98 PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90 PF9n Caution R/W Control of normal output or N-ch open-drain output (n = 0 to 15) 0 Normal output (CMOS output) 1 N-ch open-drain output When an output pin is pulled up at EVDD or higher, be sure to set
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V850ES/JG3 4.3.8 CHAPTER 4 PORT FUNCTIONS Port CM Port CM is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-11. Port CM Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H PMCCM 0 R/W Address: FFFFF04CH 0 0 PMCCM3 PMCCM3 PMCCM2 PMCCM1 PMCCM0 Specification of PCM3 pin operation mode 0 I/O port 1 HLDRQ input PMCCM2 Specification of PCM2 pin operation mode 0 I/O port 1 HLDAK output PMCCM1 Specification of PCM1 pin operation mode 0 I/O port 1 CLKOUT output PMCCM0 Specification of PCM0 pin operation mode 0 I/O port 1 WAIT input R01UH0015EJ0300 Rev.3.
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V850ES/JG3 4.3.9 CHAPTER 4 PORT FUNCTIONS Port CT Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-12. Port CT Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H PMCCT 0 R/W Address: FFFFF04AH PMCCT6 PMCCT6 PMCCT4 0 0 PMCCT1 PMCCT0 Specification of PCT6 pin operation mode 0 I/O port 1 ASTB output PMCCT4 Specification of PCT4 pin operation mode 0 I/O port 1 RD output PMCCT1 Specification of PCT1 pin operation mode 0 I/O port 1 WR1 output PMCCT0 Specification of PCT0 pin operation mode 0 I/O port 1 WR0 output R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS 4.3.10 Port DH Port DH is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-13. Port DH Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H PMCDH 0 R/W 0 PMCDHn Address: FFFFF046H PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 Specification of PDHn pin operation mode (n = 0 to 5) 0 I/O port 1 Am output (address bus output) (m = 16 to 21) R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS 4.3.11 Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-14. Port DL Alternate-Function Pins Pin Name Pin No.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) R/W Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H 15 14 13 12 11 10 9 8 PDL (PDLH) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Output data control (in output mode) (n = 0 to 15) 0 Outputs 0. 1 Outputs 1. Remarks 1. The PDL register can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H 15 R/W 14 Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H 13 12 11 10 9 8 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn Caution Specification of PDLn pin operation mode (n = 0 to 15) 0 I/O port 1 ADn I/O (address/data bus I/O) When the SMSEL bit of the EXIMC register = 1 (separa
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V850ES/JG3 4.4 CHAPTRER 4 PORT FUNCTIONS Block Diagrams Figure 4-3. Block Diagram of Type A-1 WRPM PMmn WRPORT Selector Pmn Selector Internal bus Pmn Address P-ch RD A/D input signal N-ch R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A-2 WRPM PMmn WRPORT Selector Pmn Selector Internal bus Pmn Address P-ch RD D/A output signal N-ch R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type C-1 WRPF PFmn WRPM Internal bus PMmn EVDD WRPORT Pmn P-ch Pmn EVSS Selector Selector N-ch Address RD R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D-1 WRPMC PMCmn WRPM Internal bus PMmn WRPORT Pmn Selector Selector Pmn Address RD Input signal when alternate function is used R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-2 WRPMC PMCmn WRPM Internal bus PMmn Selector Output signal when alternate function is used WRPORT Pmn Selector Selector Pmn Address RD R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D-3 WRPMC PMCmn Output enable signal of address/data bus Output buffer off signal Selector WRPM Internal bus PMmn Selector Output signal when alternate function is used WRPORT Pmn Selector Selector Pmn Address Input enable signal of address/data bus Input signal when alternate function is used RD R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type E-3 WRPF PFmn Output enable signal when alternate function is used WRPMC PMCmn PMmn EVDD Output signal when alternate function is used Selector Internal bus WRPM WRPORT P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type G-1 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector WRPORT EVDD Output signal when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type G-2 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector WRPORT EVDD Output signal when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type G-3 WRPF PFmn WRPFC PFCmn WRPMC WRPM PMmn WRPORT Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used EVDD Selector Internal bus PMCmn P-ch Pmn Pmn N-ch Selector Selector EVSS Address RD R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type G-5 WRPF PFmn Output enable signal when alternate function is used WRPFC PFCmn WRPMC WRPM PMmn Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used WRPORT EVDD Selector Internal bus PMCmn P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type G-6 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Selector Output signal when alternate function is used WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Address Note Input signal 1 when alternate function is used Input signal 2 when alternate function is used Selector RD Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type G-12 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used Selector Output signal 2 when alternate function is used EVDD WRPORT P-ch Pmn Pmn Selector N-ch RD Selector Address EVSS Note Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type L-1 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPMC Internal bus PMCmn WRPM PMmn EVDD WRPORT Pmn P-ch Pmn Selector N-ch Selector EVSS Note 2 Address RD Input signal 1 when alternate function is used Edge detection Noise elimination Notes 1. See 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type N-1 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC Internal bus PFCmn WRPMC PMCmn WRPM PMmn EVDD WRPORT Pmn P-ch Pmn Selector N-ch Selector EVSS Note 2 Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Edge detection Noise elimination Selector RD Notes 1. See 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type N-2 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC Internal bus PFCmn WRPMC PMCmn WRPM PMmn Output signal when alternate function is used EVDD Selector WRPORT Pmn P-ch Pmn Selector N-ch Selector EVSS Note 2 Address RD Input signal when alternate function is used Edge detection Noise elimination Notes 1. See 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type N-3 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn EVDD WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Note 2 Address Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Edge detection Noise elimination Selector RD Input signal 2 when alternate function is used Notes 1. See 19.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-20.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-21.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-22.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-23.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-24.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-25.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-26.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-27.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type U-12 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type U-13 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-30.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-31.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of Type AA-1 WRPF PFmn WROCDM0 External reset signal OCDM0 WRINTR INTRmnNote 1 Internal bus WRINTF INTFmnNote 1 WRPMC PMCmn WRPM PMmn EVDD WRPORT Pmn P-ch Pmn Selector Selector N-ch EVSS Note 2 Address RD N-ch Input signal when on-chip debugging Input signal when alternate function is used Edge detection Noise elimination EVSS Notes 1. See 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2.
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V850ES/JG3 4.5 CHAPTRER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. R01UH0015EJ0300 Rev.3.
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Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Rev.3.
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Pin Name P34 Rev.3.
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Pin Name P53 Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Rev.3.
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Pin Name P90 Rev.3.00 P91 Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) V850ES/JG3 R01UH0015EJ0300 Sep 30, 2010 Table 4-15.
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Pin Name P97 Rev.3.
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Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) PCM0 WAIT Input PCM0 = Setting not required PMCM0 = Setting not required PMCCM0 = 1 − − PCM1 CLKOUT Output PCM1 = Setting not required PMCM1 = Setting not required PMCCM1 = 1 − − Rev.3.
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Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Rev.3.
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V850ES/JG3 4.6 4.6.1 CHAPTRER 4 PORT FUNCTIONS Cautions Cautions on setting port pins (1) In the V850ES/JG3, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the PMCn register. In regards to this register setting sequence, note with caution the following.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below.
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V850ES/JG3 CHAPTRER 4 PORT FUNCTIONS Figure 4-33.
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V850ES/JG3 4.6.2 CHAPTRER 4 PORT FUNCTIONS Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
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V850ES/JG3 4.6.3 CHAPTRER 4 PORT FUNCTIONS Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used. The following action must be taken if on-chip debugging is not used.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JG3 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles.
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V850ES/JG3 5.2 CHAPTER 5 BUS CONTROL FUNCTION Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1.
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V850ES/JG3 5.3 CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-1.
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V850ES/JG3 5.4 CHAPTER 5 BUS CONTROL FUNCTION External Bus Interface Mode Control Function The V850ES/JG3 includes the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus interface mode control register (EXIMC) The EXIMC register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 5.5 5.5.1 CHAPTER 5 BUS CONTROL FUNCTION Bus Access Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Internal ROM (32 Bits) Internal RAM (32 Bits) External Memory (16 Bits) Bus Cycle Type Note 1 3+n Note 2 Note 1 3+n Note 2 Instruction fetch (normal access) 1 1 Instruction fetch (branch) 2 2 Operand data access 3 Note 2 1 3+n Notes 1.
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V850ES/JG3 5.5.3 CHAPTER 5 BUS CONTROL FUNCTION Access by bus size The V850ES/JG3 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits. • The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register). The operation when each of the above is accessed is described below. All data is accessed starting from the lower side.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 15 15 7 8 7 7 8 7 0 0 0 0 2n + 1 2n Byte data External data bus Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 7 7 0 0 7 7 0 0 2n + 1 2n Byte data External data bus R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Address 15 15 Address 2n + 1 8 7 8 7 15 15 8 7 8 7 Address 15 15 8 7 8 7 2n + 1 2n 0 Second access 2n + 2 2n 0 0 Halfword data External data bus 0 Halfword data 0 External data bus 0 Halfword data External data bus (b) 8-bit data bus width <1> Access to even address (2n) First access 15 <2> Acc
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access 31 31 24 23 24 23 Address 16 15 15 8 7 8 7 0 0 Address 16 15 15 8 7 8 7 0 0 4n + 1 4n + 3 4n Word data External data bus 4n + 2 Word data External data bus <2> Access to address (4n + 1) First access Second access Third access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 0 Address 16 15 15 8 7 8 7 8 7 0 0
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access 31 31 24 23 24 23 Address 16 15 15 8 7 8 7 Address 16 15 15 8 7 8 7 4n + 3 4n + 5 4n + 2 0 0 4n + 4 0 Word data External data bus 0 Word data External data bus <4> Access to address (4n + 3) First access Second access Third access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 0 Address 16 15 15 8 7 8 7 8 7 0 0 0 4n + 3 Address
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 0 0 Address 8 7 7 0 0 4n Word data External data bus Address 8 7 7 0 0 4n + 1 Word data External data bus Address 8 7 7 0 0 4n + 2 Word data External data bus 4n + 3 Word data External data bus <2> Access to address (4n + 1) First access Se
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n + 2 0 0 Word data External data bus Address 8 7 7 4n + 3 0 0 Word data External data bus 8 7 Address 7 4n + 4 0 0 Word data External data bus 8 7 Address 7 4n + 5 0 0 Word data External data bus <4> Access to address (4n + 3) First access Secon
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V850ES/JG3 5.6 5.6.1 CHAPTER 5 BUS CONTROL FUNCTION Wait Function Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. The number of wait states can be programmed by using the DWC0 register . Immediately after system reset, 7 data wait states are inserted for all the blocks.
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V850ES/JG3 5.6.2 CHAPTER 5 BUS CONTROL FUNCTION External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set to alternate function, the external wait function is enabled.
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V850ES/JG3 5.6.3 CHAPTER 5 BUS CONTROL FUNCTION Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will be inserted in the bus cycle. Figure 5-3.
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V850ES/JG3 5.6.4 CHAPTER 5 BUS CONTROL FUNCTION Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each memory block area (memory blocks 0 to 3). If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an address hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
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V850ES/JG3 5.7 CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected as the memory block in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
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V850ES/JG3 5.8 CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
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V850ES/JG3 5.8.2 CHAPTER 5 BUS CONTROL FUNCTION Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = 0 Bus hold status <6> HLDRQ = 1 acknowledged <7> HLDAK = 1 <8> Bus cycle start request inhibition released Normal status <9> Bus cycle starts HLDRQ (input) HLDAK (output) <1> <2> <3><4> <5> 5.8.
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V850ES/JG3 5.9 CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive). An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A21 to A16 A1 A2 A3 D2 A3 ASTB WAIT AD15 to AD0 A1 D1 A2 RD Idle state Programmable External wait wait 8-bit access Odd address AD15 to AD8 Active Hi-Z Hi-Z Active AD7 to AD0 Remark Even address The broken lines indicate high impedance. Figure 5-5.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 T1 CLKOUT A21 to A16 A1 A2 A3 D2 A3 ASTB WAIT AD15 to AD0 WR1, WR0 A1 D1 11 00 A2 11 11 00 11 Programmable External wait wait 8-bit access Odd address Even address Active Undefined Undefined Active AD15 to AD8 AD7 to AD0 01 WR1, WR0 10 Figure 5-7.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 TINote TH TH TH TH TINote T1 T2 T3 CLKOUT HLDRQ HLDAK A21 to A16 AD15 to AD0 A1 A1 Undefined Undefined D1 Undefined Undefined A2 A2 D2 ASTB RD Note This idle state (TI) does not depend on the BCC register settings. Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode. 2. The broken lines indicate high impedance. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T2 T1 T1 TW TW T2 TI T1 T2 CLKOUT WAIT A1 A21 to A0 A2 A3 RD AD15 to AD0 D1 D2 D3 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Hi-Z Hi-Z Active AD7 to AD0 Remark Idle state The broken lines indicate high impedance. Figure 5-10.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T2 T1 T1 TW TW T2 T1 T2 CLKOUT WAIT A1 A21 to A0 WR1, WR0 11 A2 00 AD15 to AD0 11 11 A3 00 D1 11 00 D2 11 D3 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined AD7 to AD0 Undefined 01 WR1, WR0 Remark Active 10 The broken lines indicate high impedance. Figure 5-12.
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V850ES/JG3 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) T1 T2 T1 T2 TINote TH TH TH TINote TH T1 T2 CLKOUT HLDRQ HLDAK A21 to A0 A1 AD7 to AD0 WR1, WR0 D1 11 Undefined A2 Undefined A3 D2 10 11 10 D3 11 11 10 11 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance. Figure 5-14.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode fX = 2.5 to 10 MHz (fXX = 2.5 to 10 MHz) • In PLL mode fX = 2.5 to 5 MHz (×4: fXX = 10 to 20 MHz) fX = 2.5 to 4 MHz (×8: fXX = 20 to 32 MHz) Subclock oscillator • fXT = 32.
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V850ES/JG3 6.2 CHAPTER 6 CLOCK GENERATION FUNCTION Configuration Figure 6-1.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main resonator oscillates the following frequencies (fX). • In clock-through mode fX = 2.5 to 10 MHz • In PLL mode fX = 2.5 to 5 MHz (×4) fX = 2.5 to 4 MHz (×8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator.
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V850ES/JG3 6.3 CHAPTER 6 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION After reset: 03H R/W Address: FFFFF828H < > < > PCC FRC MCK MFRC FRC Note CLS < > CK3 CK2 CK1 CK0 Use of subclock on-chip feedback resistor 0 Used 1 Not used MCK Main clock oscillator control 0 Oscillation enabled 1 Oscillation stopped • Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/fXT (1/subclock frequency) <3> MCK bit ← 1: Set the MCK bit to 1 only when stopping the main clock.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 bit ← 0: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <4> Main clock operation: It takes the following time after the CK3 bit is set until main clock operation is started. Max.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF80CH < > RCM 0 0 0 RSTOP 0 0 0 0 RSTOP Oscillation/stop of internal oscillator 0 Internal oscillator oscillation 1 Internal oscillator stopped Cautions 1.
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V850ES/JG3 6.4 6.4.1 CHAPTER 6 CLOCK GENERATION FUNCTION Operation Operation of each clock The following table shows the operation status of each clock. Table 6-1.
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V850ES/JG3 6.5 6.5.1 CHAPTER 6 CLOCK GENERATION FUNCTION PLL Function Overview In the V850ES/JG3, an operating clock that is 4 or 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions. When PLL function is used (×4): Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz) When PLL function is used (×8): Input clock = 2.5 to 4 MHz (output: 20 to 32 MHz) Clock-through mode: 6.5.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.7 Special registers). The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 0AH.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status. The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/JG3 has nine timer/event counter channels, TMP0 to TMP5. 7.1 Overview An outline of TMPn is shown below.
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V850ES/JG3 7.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration TMPn includes the following hardware. Table 7-1.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at this time, 0000H is read. Reset sets the TPnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
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V850ES/JG3 7.4 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Registers The registers that control TMPn are as follows. • TMPn control register 0 (TPnCTL0) • TMPn control register 1 (TPnCTL1) • TMPn I/O control register 0 (TPnIOC0) • TMPn I/O control register 1 (TPnIOC1) • TMPn I/O control register 2 (TPnIOC2) • TMPn option register 0 (TPnOPT0) • TMPn capture/compare register 0 (TPnCCR0) • TMPn capture/compare register 1 (TPnCCR1) • TMPn counter read buffer register (TPnCNT) Remarks 1.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TPnCTL0 register by software.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H R/W Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H, TP4CTL1 FFFFF5D1H, TP5CTL1 FFFFF5E1H TPnCTL1 7 <6> <5> 4 3 0 TPnEST TPnEEE 0 0 2 1 0 TPnMD2 TPnMD1 TPnMD0 (n = 0 to 5) TPnEST Software trigger control 0 − 1 Generate a valid signal for external trigger input. • In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TPnEST bit as the trigger.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit. In the pulse width measurement mode, the TPnCCR0 register can be used only as a capture register.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. If TOPn0 pin output is enabled at this time, the output of the TOPn0 pin is inverted.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit. In the pulse width measurement mode, the TPnCCR1 register can be used only as a capture register.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. If TOPn1 pin output is enabled at this time, the output of the TOPn1 pin is inverted.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TPnCNT register is cleared to 0000H when the TPnCE bit = 0.
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V850ES/JG3 7.5 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Operation TMPn can perform the following operations. TPnCTL1.
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V850ES/JG3 7.5.1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the TPnCTL0.TPnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOPn0 pin. Usually, the TPnCCR1 register is not used in the interval timer mode. Figure 7-2.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-5.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOPn0 pin is inverted. The value of the 16-bit counter is always 0000H.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted. At this time, an overflow interrupt request signal (INTTPnOV) is not generated, nor is the overflow flag (TPnOPT0.TPnOVF bit) set to 1.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 7-6. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Output controller Match signal TOPn1 pin INTTPnCC1 signal Clear Count clock selection 16-bit counter Match signal TPnCE bit Output controller TOPn0 pin INTTPnCC0 signal CCR0 buffer register TPnCCR0 register Remark n = 0 to 5 R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted. The TOPn1 pin outputs a square wave with the same cycle as that output by the TOPn0 pin. Figure 7-7.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed. Figure 7-8.
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V850ES/JG3 7.5.2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted. The TOPn0 pin cannot be used. Usually, the TPnCCR1 register is not used in the external event count mode. Figure 7-9.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare register 0 (TPnCCR0) If D0 is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTPnCC0) is generated when the number of external event counts reaches (D0 + 1).
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-12.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TPnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 000, TPnCTL1.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register Figure 7-13. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal INTTPnCC1 signal Clear Edge detector TIPn0 pin 16-bit counter Match signal TPnCE bit INTTPnCC0 signal CCR0 buffer register TPnCCR0 register Remark n = 0 to 5 If the set value of the TPnCCR1 register is smaller than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match. Figure 7-15. Timing Chart When D01 < D11 FFFFH D01 D01 D01 D01 16-bit counter 0000H TPnCE bit TPnCCR0 register D01 INTTPnCC0 signal D11 TPnCCR1 register INTTPnCC1 signal Remark L n = 0 to 5 R01UH0015EJ0300 Rev.
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V850ES/JG3 7.5.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-17.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Register Setting for Operation in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-19.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-19.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write the same value to the TPnCCR1 register.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
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V850ES/JG3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
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V850ES/JG3 7.5.4 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin. Instead of the external trigger, a software trigger can also be generated to output the pulse.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-23.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
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V850ES/JG3 7.5.5 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOPn0 pin. Figure 7-24.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting for Operation in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-27.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow START Setting of TPnCCR1 register Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
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V850ES/JG3 7.5.6 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits. Figure 7-28.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 TPnCKS2 TPnCKS1 TPnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnOPT0 register, TPnCCR0 register, TPnCCR1 register TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-33.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC1 register, TPnOPT0 register TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TPnCE bit INTTPnOV signal TPnOVF bit TPnOVF0 flagNote TIPn0 pin input D01 D00 TPnCCR0 register TPnOVF1 flagNote TIPn1 pin input D11 D10 TPnCCR1 register <1> <2> <3> <4> <5> <6> Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TPnCE bit INTTPnOV signal TPnOVF bit TPnOVF0 flagNote TIPn0 pin input D01 D00 TPnCCR0 register TPnOVF1 flagNote TIPn1 pin input D11 D10 TPnCCR1 register <1> <2> <3> <4> <5> <6> Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TPnCE bit TIPnm pin input TPnCCRm register Dm0 Dm1 INTTPnOV signal TPnOVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input). <2> An overflow occurs.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3 7.5.7 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register 0000H D0 D1 D2 D3 INTTPnCCm signal INTTPnOV signal TPnOVF bit Remark Cleared to 0 by CLR instruction n = 0 to 5 m = 0, 1 When the TPnCE bit is set to 1, the 16-bit counter starts counting.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOPT0 0 0 0 0 TPnOVF 0 0 0 0/1 Overflow flag (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-37.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3 7.5.8 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer output operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 7-4.
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V850ES/JG3 7.6 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Selector Function In the V850ES/JG3, the capture trigger input for TMP can be selected from the input signal via the port/timer alternatefunction pin and the peripheral I/O (TMP/UARTA) input signal. This function makes the following possible.
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V850ES/JG3 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for TMP1. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 7.7 CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TPnCCR0 and TPnCCR1 registers if the capture trigger is input immediately after the TPnCE bit is set to 1.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850ES/JG3 incorporates TMQ0. 8.1 Overview An outline of TMQ0 is shown below. • Clock selection: 8 ways • Capture/trigger input pins: 4 • External event count input pins: 1 • External trigger input pins: 1 • Timer/counters: 1 • Capture/compare registers: 4 • Capture/compare match interrupt request signals: 4 • Timer output pins: 4 8.
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V850ES/JG3 8.3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Configuration TMQ0 includes the following hardware. Table 8-1.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TQ0CNT register. When the TQ0CTL0.TQ0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TQ0CNT register is read at this time, 0000H is read. Reset sets the TQ0CE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
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V850ES/JG3 8.4 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers The registers that control TMQ0 are as follows.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQ0CTL0 register by software.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) TMQ0 control register 1 (TQ0CTL1) The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 TQ0CTL1 0 R/W <6> Address: <5> TQ0EST TQ0EEE FFFFF541H 4 3 0 0 2 0 TQ0MD2 TQ0MD1 TQ0MD0 TQ0EST Software trigger control 0 − 1 1 Generate a valid signal for external trigger input.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output (TOQ00 to TOQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQ00 pin) and external trigger input signal (TIQ00 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS0 bit. In the pulse width measurement mode, the TQ0CCR0 register can be used only as a capture register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR0 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated. If TOQ00 pin output is enabled at this time, the output of the TOQ00 pin is inverted.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS1 bit. In the pulse width measurement mode, the TQ0CCR1 register can be used only as a capture register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR1 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated. If TOQ01 pin output is enabled at this time, the output of the TOQ01 pin is inverted.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS2 bit. In the pulse width measurement mode, the TQ0CCR2 register can be used only as a capture register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR2 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated. If TOQ02 pin output is enabled at this time, the output of the TOQ02 pin is inverted.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS3 bit. In the pulse width measurement mode, the TQ0CCR3 register can be used only as a capture register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR3 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated. If TOQ03 pin output is enabled at this time, the output of the TOQ03 pin is inverted.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQ0 counter read buffer register (TQ0CNT) The TQ0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQ0CTL0.TQ0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TQ0CNT register is cleared to 0000H when the TQ0CE bit = 0.
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V850ES/JG3 8.5 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Operation TMQ0 can perform the following operations. TQ0CTL1.
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V850ES/JG3 8.5.1 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQ0CC0) is generated at the specified interval if the TQ0CTL0.TQ0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOQ00 pin. Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. Figure 8-2.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-4.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 8-5.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing (a) Operation if TQ0CCR0 register is set to 0000H If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOQ00 pin is inverted. The value of the 16-bit counter is always 0000H.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQ0CCR0 register To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-6.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is less than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. At the same time, the output of the TOPQ0k pin is inverted. The TOQ0k pin outputs a square wave with the same cycle as that output by the TOQ00 pin. Remark k = 1 to 3 Figure 8-7.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the count value of the 16-bit counter does not match the value of the TQ0CCRk register. Consequently, the INTTQ0CCk signal is not generated, nor is the output of the TOQ0k pin changed. Remark k = 1 to 3 Figure 8-8.
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V850ES/JG3 8.5.2 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) External event count mode (TQ0MD2 to TQ0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified number of edges have been counted. The TOQ00 pin cannot be used. Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. Figure 8-9.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2) (f) TMQ0 capture/compare register 0 (TQ0CCR0) If D0 is set to the TQ0CCR0 register, the counter is cleared and a compare match interrupt request signal (INTTQ0CC0) is generated when the number of external event counts reaches (D0 + 1).
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 8-12.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TQ0CCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 000, TQ0CTL1.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-13.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. Remark k = 1 to 3 Figure 8-14.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRk register do not match. Remark k = 1 to 3 Figure 8-15.
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V850ES/JG3 8.5.3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter Q starts counting, and outputs a PWM waveform from the TOQ01 to TOQ03 pins.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-17.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOQ00 pin is inverted. The TOQ0k pin outputs a high-level regardless of the status (high/low) when a trigger is generated.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-18.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 8-19.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-19.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTQ0CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0k pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0k pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection.
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V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
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V850ES/JG3 8.5.4 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and outputs a one-shot pulse from the TOQ01 to TOQ03 pins. Instead of the external trigger, a software trigger can also be generated to output the pulse.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-21.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D0 is set to the TQ0CCR0 register and Dk to the TQ0CCRk register, the active level width and output delay period of the one-shot pulse are as follows.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode Figure 8-23.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-23.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRm register To change the set value of the TQ0CCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCk) The generation timing of the INTTQ0CCk signal in the one-shot pulse output mode is different from other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
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V850ES/JG3 8.5.5 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 pins when the TQ0CTL0.TQ0CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOQ00 pin. Figure 8-24.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-25.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting for Operation in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D0 is set to the TQ0CCR0 register and Dk to the TQ0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = Dk × Count clock cycle Remarks 1.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 8-27.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow START <4> TQ0CCR1 to TQ0CCR3 register setting change flow Setting of TQ0CCR2, TQ0CCR3 registers Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 register, TQ0CCR0 to TQ0CCR3 registers TQ0CE bit = 1 Initial setting of these registers is performed before setting the TQ0CE bit to 1.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC1 signal is detected.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the PWM output mode differs from the timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
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V850ES/JG3 8.5.6 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. At this time, the TQ0CCRm register can be used as a compare register or a capture register, depending on the setting of the TQ0OPT0.TQ0CCS0 and TQ0OPT0.TQ0CCS1 bits. Remark m = 0 to 3 Figure 8-28.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register, a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal (INTTQ0CCm) is generated. The 16-bit counter continues counting in synchronization with the count clock.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-32.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 register, TQ0OPT0 register, TQ0CCR0 to TQ0CCR3 registers TQ0CE bit = 1 Initial setting of these registers is performed before setting the TQ0CE bit to 1.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 8-33.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC1 register, TQ0OPT0 register TQ0CE bit = 1 Initial setting of these registers is performed before setting the TQ0CE bit to 1.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQ0CCm signal has been detected.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQ0CCRm register must be re-set in the interrupt servicing that is executed when the INTTQ0CCm signal is detected. The set value for re-setting the TQ0CCRm register can be calculated by the following expression, where “Dm” is the interval period.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCm signal has been detected and for calculating an interval.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRm register in synchronization with the INTTQ0CCm signal, and calculating the difference between the read value and the previously read value. Remark m = 0 to 3 R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit TQ0OVF0 flagNote TIQ00 pin input D01 D00 TQ0CCR0 register TQ0OVF1 flagNote TIQ01 pin input D11 D10 TQ0CCR1 register <1> <2> <3> <4> <5> <6> Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit TQ0OVF0 flagNote TIQ00 pin input D01 D00 TQ0CCR0 register TQ0OVF1 flagNote TIQ01 pin input D11 D10 TQ0CCR1 register <1> <2> <3> <4> <5> <6> Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register Dm0 Dm1 INTTQ0OV signal TQ0OVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TQ0CCRm register (setting of the default value of the TIQ0m pin input). <2> An overflow occurs.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8bit data (bit 0 is 0) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3 8.5.7 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register 0000H D0 D1 D2 D3 INTTQ0CCm signal INTTQ0OV signal TQ0OVF bit Remark Cleared to 0 by CLR instruction m = 0 to 3 When the TQ0CE bit is set to 1, the 16-bit counter starts counting.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIQ0m pin is detected. Remarks 1.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 8-37.
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V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8bit data (bit 0 is “0”) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
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V850ES/JG3 8.5.8 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer output operations The following table shows the operations and output levels of the TOQ00 to TOQ03 pins. Table 8-6.
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V850ES/JG3 8.6 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TQ0CCR0, TQ0CCR1, TQ0CCR2, and TQ0CCR3 registers if the capture trigger is input immediately after the TQ0CE bit is set to 1.
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V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.1 Overview • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.) • Compare match interrupt × 1 Timer M supports only the clear & start mode. The free-running timer mode is not supported. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 9.2 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMM0 includes the following hardware. Table 9-1. Configuration of TMM0 Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Figure 9-1.
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V850ES/JG3 9.3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TM0CTL0 register by software.
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V850ES/JG3 9.4 Operation Caution 9.4.1 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Do not set the TM0CMP0 register to FFFFH. Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the TM0CTL0.TM0CE bit is set to 1. Figure 9-2. Configuration of Interval Timer Clear Count clock selection INTTM0EQ0 signal 16-bit counter Match signal TM0CE bit TM0CMP0 register Figure 9-3.
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V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Figure 9-4. Register Setting for Interval Timer Mode Operation (a) TMM0 control register 0 (TM0CTL0) TM0CE TM0CTL0 0/1 TM0CKS2 TM0CKS1 TM0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMM0 compare register 0 (TM0CMP0) If the TM0CMP0 register is set to D, the interval is as follows. Interval = (D + 1) × Count clock cycle R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH D 16-bit counter D D 0000H TM0CE bit TM0CMP0 register D INTTM0EQ0 signal <1> <2> <1> Count operation start flow START Register initial setting TM0CTL0 register (TM0CKS0 to TM0CKS2 bits) TM0CMP0 register TM0CE bit = 1 Initial setting of these registers is performed before setting the TM0CE bit to 1.
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V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TM0CMP0 register to FFFFH. (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H.
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V850ES/JG3 9.4.2 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS CHAPTER 10 WATCH TIMER FUNCTIONS 10.1 Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. • Interval timer: An interrupt request signal (INTWTI) is generated at set intervals. The watch timer and interval timer functions can be used at the same time. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS 10.2 Configuration The block diagram of the watch timer is shown below. Figure 10-1.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS (1) Clock control This block controls supplying and stopping the operating clock (fX) when the watch timer operates on the main clock. (2) 3-bit prescaler This prescaler divides fX to generate fX/2, fX/4, or fX/8. (3) 8-bit counter This 8-bit counter counts the source clock (fBGCS). (4) 11-bit prescaler This prescaler divides fW to generate a clock of fW/24 to fW/211.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS 10.3 Control Registers The following registers are provided for the watch timer. • Prescaler mode register 0 (PRSM0) • Prescaler compare register 0 (PRSCM0) • Watch timer operation mode register (WTM) (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H PRSCM0 R/W Address: FFFFF8B1H PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1. Do not rewrite the PRSCM0 register during watch timer operation. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 3.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS (3) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. Set the PRSM0 register before setting the WTM register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS (2/2) WTM7 WTM3 Selection of set time of watch flag WTM2 14 0 0 0 2 /fW (0.5 s: fW = fXT) 0 0 1 213/fW (0.25 s: fW = fXT) 0 1 0 25/fW (977 μ s: fW = fXT) 0 1 1 24/fW (488 μ s: fW = fXT) 1 0 0 214/fW (0.5 s: fW = fBRG) 1 0 1 213/fW (0.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS 10.4 Operation 10.4.1 Operation as watch timer The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz) or main clock. The count operation starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11. When the WTM0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS 10.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a preset count value. The interval time can be selected by the WTM4 to WTM7 bits of the WTM register. Table 10-1. Interval Time of Interval Timer WTM7 0 0 0 WTM6 WTM5 0 0 0 0 0 1 WTM4 Interval Time 0 2 × 1/fw 488 μs (operating at fW = fXT = 32.
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V850ES/JG3 CHAPTER 10 WATCH TIMER FUNCTIONS Figure 10-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Overflow Start Overflow Count clock fW or fW/29 Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Interval time (T) nT nT Remarks 1. When 0.5 seconds of the watch timer interrupt time is set. 2.
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V850ES/JG3 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.1 Functions Watchdog timer 2 has the following functions.
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V850ES/JG3 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 11-1.
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V850ES/JG3 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. Reset sets this register to 67H. Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.
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V850ES/JG3 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 Table 11-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) 12 41.0 ms 18.6 ms 10.2 ms 13 81.9 ms 37.2 ms 20.5 ms 14 163.8 ms 74.5 ms 41.0 ms 15 327.7 ms 148.9 ms 81.9 ms 16 655.4 ms 297.9 ms 163.8 ms 17 1,310.7 ms 595.8 ms 327.7 ms 18 2,621.4 ms 1,191.6 ms 655.4 ms 19 5,242.9 ms 2,383.1 ms 1,310.
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V850ES/JG3 11.4 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this, the operation of watchdog timer 2 cannot be stopped.
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.1 Function The real-time output function transfers preset data to the RTBL0 and RTBH0 registers, and then transfers this data by hardware to an external device via the output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called the real-time output function (RTO).
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration The block diagram of RTO is shown below. Internal bus Figure 12-1.
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data. These registers are mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPC0.
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Tables 12-3 and 12-4. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits). Of the transferred data, only the data of the bits for which real-time output is enabled by the RTPM0 register is output from the RTP00 to RTP05 bits.
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V850ES/JG3 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 5 Set the PFC5.PFC5m bit and PFCE5.PFCE5m bit to 1, and then set the PMC5.PMC5m bit to 1 (m = 0 to 5). • Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register. • Channel configuration: Select the trigger and valid edge. Set the RTPC0.EXTR0, RTPC0.BYTE0, and RTPC0.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 analog input signal channels (ANI0 to ANI11). The A/D converter has the following features. 10-bit resolution 12 channels Successive approximation method Operating voltage: AVREF0 = 3.0 to 3.6 V Analog input voltage: 0 V to AVREF0 The following functions are provided as operation modes.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.3 Configuration The block diagram of the A/D converter is shown below. Figure 13-1.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (1) Successive approximation register (SAR) The SAR register compares the voltage value of the analog input signal with the output voltage (compare voltage) value of the compare voltage generation DAC, and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been held down to the least significant bit (LSB) (i.e.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (13) ANI0 to ANI11 pins These are analog input pins for the 12 A/D converter channels and are used to input analog signals to be converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be used as input port pins.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (2/2) Trigger mode specification ADA0TMD 0 Software trigger mode 1 External trigger mode/timer trigger mode A/D converter status display ADA0EF 0 A/D conversion stopped 1 A/D conversion in progress Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ADA0M1 ADA0HS1 R/W 0 Address: FFFFF201H 0 0 ADA0FR3 ADA0FR2 ADA0FR1 ADA0FR0 ADA0HS1 Specification of normal conversion mode/high-speed mode (A/D conversion time) 0 Normal conversion mode 1 High-speed conversion mode Cautions 1.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) A/D Conversion Time ADA0FR3 to ADA0FR0 Stabilization Time + Conversion Bits Time + Wait Time fXX = 32 MHz fXX = 20 MHz fXX = 16 MHz fXX = 4 MHz Trigger Response Time 0000 66/fXX (13/fXX + 26/fXX + 27/fXX) Setting prohibited Setting prohibited Setting prohibited 16.50 μs 3/fXX 0001 131/fXX (26/fXX + 52/fXX + 53/fXX) Setting prohibited 6.55 μs 8.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0FR3 to ADA0FR0 Bits A/D Conversion Time Conversion Time fXX = 32 MHz fXX = 20 MHz fXX = 16 MHz Trigger fXX = 4 MHz Response (+ Stabilization Time) Time 0000 26/fXX (+ 13/fXX) Setting prohibited Setting prohibited Setting prohibited 6.5 μs (+ 3.25 μs) 3/fXX 0010 52/fXX (+ 26/fXX) Setting prohibited 2.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (4) A/D converter channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read from the higher 10 bits of the ADA0CRn register, and 0 is read from the lower 6 bits.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (ADA0CRn register) is as follows. SAR = INT ( VIN AVREF0 × 1,024 + 0.5) ADA0CRNote = SAR × 64 Or, (SAR − 0.5) × AVREF0 1,024 ≤ VIN < (SAR + 0.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 R/W 6 Address: FFFFF205H 5 4 3 2 1 0 ADA0PFT Caution When writing data to the ADA0PFT register in the following modes, stop the A/D conversion by clearing the AD0M0.ADA0CE bit to 0.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.5.2 Conversion operation timing Figure 13-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Setup Processing state Sampling Second conversion A/D conversion Wait Setup Conversion time Wait time Sampling INTAD signal Stabilization time 2/fXX (MAX.) Sampling time 0.5/fXX (2) Operation in high-speed conversion mode (ADA0HS1 bit = 1) ADA0M0.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.5.3 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits. (1) Software trigger mode When the ADA0M0.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer. The INTTP2CC0 or INTTP2CC1 signal is selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER Figure 13-5.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis. When A/D conversion has been completed once, the INTAD signal is generated.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER Figure 13-7.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter). • When the ADA0PFE bit = 1 and when the ADA0PFM.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER Figure 13-9.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER Figure 13-11.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI11 pins Input the voltage within the specified range to the ANI0 to ANI11 pins.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (7) AVREF0 pin (a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternatefunction ports. In an application where a backup power supply is used, be sure to supply the same voltage as VDD to the AVREF0 pin as shown in Figure 13-15. (b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (10) High-speed conversion mode In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input during the stabilization time are prohibited.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale range).
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable. This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. Figure 13-17.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 13-19. Full-Scale Error Digital output (lower 3 bits) Full-scale error 111 100 011 010 000 0 AVREF0 − 3 AVREF0 − 2 AVREF0 − 1 AVREF0 Analog input (LSB) (6) Differential linearity error Ideally, the width to output a specific code is 1 LSB.
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V850ES/JG3 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. Figure 13-21. Integral Linearity Error 1......1 Digital output Ideal line Integral linearity error 0......
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V850ES/JG3 CHAPTER 14 D/A CONVERTER CHAPTER 14 D/A CONVERTER 14.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DA0CS0, DA0CS1) R-2R ladder method Settling time: 3 μs max. (when AVREF1 is 3.0 to 3.6 V and external load is 20 pF) Analog output voltage: AVREF1 × m/256 (m = 0 to 255; value set to DA0CSn register) Operation modes: Normal mode, real-time output mode Remark n = 0, 1 14.2 Configuration The D/A converter configuration is shown below. Figure 14-1.
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V850ES/JG3 CHAPTER 14 D/A CONVERTER The D/A converter includes the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 14.3 Registers The registers that control the D/A converter are as follows.
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V850ES/JG3 CHAPTER 14 D/A CONVERTER (2) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H DA0CSn Caution R/W Address: DA0CS0 FFFFF280H, DA0CS1 FFFFF281H DA0CSn7 DA0CSn6 DA0CSn5 DA0CSn4 DA0CSn3 DA0CSn2 DA0CSn1 DA0CSn0 In the real-time output mode (DA0M.
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V850ES/JG3 CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MDn bit to 0 (normal mode). <2> Set the analog voltage value to be output to the ANOn pin to the DA0CSn register. Steps <1> and <2> above constitute the initial settings. <3> Set the DA0M.DA0CEn bit to 1 (D/A conversion enable).
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V850ES/JG3 CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/JG3. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode. (2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1 Mode Switching of UARTA and Other Serial Interfaces 15.1.1 CSIB4 and UARTA0 mode switching In the V850ES/JG3, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA0 in advance, using the PMC3 and PFC3 registers, before use.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 2 15.1.2 UARTA2 and I C00 mode switching In the V850ES/JG3, UARTA2 and I2C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA2 in advance, using the PMC3 and PFC3 registers, before use. Caution The transmit/receive operation of UARTA2 and I2C00 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 15-2.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 2 15.1.3 UARTA1 and I C02 mode switching In the V850ES/JG3, UARTA1 and I2C02 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA1 in advance, using the PMC9, PFC9, and PMCE9 registers, before use. Caution The transmit/receive operation of UARTA1 and I2C02 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 15-3.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.3 Configuration The block diagram of the UARTAn is shown below. Figure 15-4.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn. (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnDIR Transfer direction selection 0 MSB-first transfer 1 LSB-first transfer • This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. • When transmission and reception are performed in the LIN format, set the UAnDIR bit to 1.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register. This register can be read or written in 8-bit or 1-bit units.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSLS2 UAnSLS1 UAnSLS0 SBF transmit length selection 1 0 1 13-bit output (reset value) 1 1 0 14-bit output 1 1 1 15-bit output 0 0 0 16-bit output 0 0 1 17-bit output 0 1 0 18-bit output 0 1 1 19-bit output 1 0 0 20-bit output This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H R/W Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H UAnSTR <7> 6 5 4 3 <2> <1> <0> UAnTSF 0 0 0 0 UAnPE UAnFE UAnOVE (n = 0 to 2) UAnTSF Transfer status flag 0 • When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception complete interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal. Table 15-2.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UAnCTL0 register.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-5.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 SBF transmission/reception format The V850ES/JG3 has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-7. LIN Reception Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field DATA field Note 2 13 bits SF reception ID reception Data transmission DATA field Check SUM field LIN bus RXDAn (input) Disable Enable Data Note 5 transmission Data transmission SBF reception Note 3 Reception interrupt (INTUAnR) Note 1 Edge detection Note 4 Capture timer Disable Enable Notes 1.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is output. A transmission enable interrupt request signal (INTUAnT) is generated upon SBF transmission start.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 SBF reception The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit detection is performed.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-9. SBF Reception (2/2) (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) RXDAn 1 2 3 4 5 6 7 8 9 10 10.5 UAnSRF INTUAnR interrupt R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register. The start bit, parity bit, and stop bit are automatically added.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT). An efficient communication rate is realized by writing the data to be transmitted next to the UAnTX register during transfer.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-12.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine. First the rising edge of the RXDAn pin is detected and sampling is started at the falling edge.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output when an error occurs. It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) When reception errors occur, perform the following procedures depending upon the kind of error. • Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit. • Framing error A baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data. Therefore, data not exceeding 1 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 15-15). See 15.7 (1) (a) Base clock regarding the base clock.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. There is an 8-bit counter for transmission and another one for reception. (1) Baud rate generator configuration Figure 15-16.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH. Caution Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to 00 before rewriting the UAnCTL2 register.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. Baud rate = fUCLK 2×k [bps] When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate using the above equation). Baud rate = fXX m+1 2 Remark ×k [bps] fUCLK = Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits fXX: Main clock frequency m = Value set using the UAnCTL1.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) To set the baud rate, perform the following calculation for setting the UAnCTL1 and UAnCTL2 registers (when using internal clock). <1> Set k to fxx/(2 × target baud rate) and m to 0. <2> If k is 256 or greater (k ≥ 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> Repeat Step <2> until k becomes less than 256 (k < 256). <4> Round off the first decimal point of k to the nearest whole number.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation. Figure 15-17.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. 1 BRmax = (FLmin/11)− = 22k Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 10 k+2 × FLmax = 11 × FL − 2×k 11 FLmax = 21k − 2 × FL = 21k − 2 2×k FL FL × 11 20 k Therefore, the minimum baud rate that can be received by the destination is as follows.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. Figure 15-18.
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V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.8 Cautions (1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped. However, the operation is not guaranteed after the clock supply is resumed.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1 Mode Switching of CSIB and Other Serial Interfaces 16.1.1 CSIB4 and UARTA0 mode switching In the V850ES/JG3, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB4, in advance, using the PMC3 and PFC3 registers, before use.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 2 16.1.2 CSIB0 and I C01 mode switching In the V850ES/JG3, CSIB0 and I2C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB0 in advance, using the PMC4 and PFC4 registers, before use. Caution The transmit/receive operation of CSIB0 and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.3 Configuration The following shows the block diagram of CSIBn. Figure 16-3.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register. Reset sets this register to 0000H.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.4 Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/3) CBnDIRNote Specification of transfer direction mode (MSB/LSB) 0 MSB-first transfer 1 LSB-first transfer CBnTMSNote Transfer mode specification 0 Single transfer mode 1 Continuous transfer mode [In single transfer mode] The reception complete interrupt request signal (INTCBnR) is generated. Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt request signal (INTCBnT) is not generated.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3/3) CBnSCE Specification of start transfer disable/enable 0 Communication start trigger invalid 1 Communication start trigger valid • In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode The setting of the CBnSCE bit has no influence on communication operation.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset sets this register to 00H. In addition to reset input, the CBnSTR register can be initialized by clearing (0) the CBnCTL0.CBnPWR bit.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. • Reception complete interrupt request signal (INTCBnR) • Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. Table 16-2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6 Operation 16.6.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 (5) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (7) Bit 2 Bit 1 Bit 0 (8) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 00H to the CBnCTL1 register, and select communication type 1, commu
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (5) Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (7) Bit 2 Bit 1 Bit 0 (8) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 07H to the CBnCTL1 register, and select communication type 1, c
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal INTCBnR signal L SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 Bit 5 (6) Bit 4 Bit 3 Bit 2 (7) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (8) (9) (10) (11) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register ← 00H CBnCTL2 register ← 00H CBnCTL0 register ← A3H (4) CBnRX register dummy read (5) Start reception No INTCBnR interrupt generated? Yes CBnOVE bit = 1? (CBnSTR) No (6) Yes (8) Is data being received last data? CBnSCE bit = 0 (CBnCTL0) No (7) Yes (9) Read CBnRX register (12) CBnOVE bit = 0 (CBnSTR) (8) CBnSCE bit = 0 (CBnCTL0) (9) (9) Read CBnRX register (10) IN
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SOBn pin L SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register ← 00H CBnCTL2 register ← 00H CBnCTL0 register ← E3H (4) Write CBnTX register (5) Start transmission/reception (6), (11) INTCBnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CBnTX register INTCBnR interrupt generated? (8) Yes No (9) CBnOVE bit = 1? (CBnSTR) (10) Read CBnRX register Yes (13) (13) Read CBnRX register Is
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 00H to the CBnCTL1 r
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CBnTX register.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 (6) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 Bit 7 (8) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (9) Bit 0 (10) (11) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register ← 07H CBnCTL2 register ← 00H CBnCTL0 register ← A3H (4) CBnRX register dummy read (4) SCKBn pin input started? No Yes (5) Reception start No INTCBnR interrupt generated? Yes CBnOVE bit = 1? (CBnSTR) No (6) Yes (8) (9) (12) CBnSCE bit = 0 (CBnCTL0) Is data being received last data? Read CBnRX register No (7) Yes (8) CBnSCE bit = 0 (CBnCTL0) (9) Read CBnRX registe
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register ← 07H CBnCTL2 register ← 00H CBnCTL0 register ← E3H (4) Write CBnTX register (4) SCKBn pin input started? No Yes (5) (6), (11) Start transmission/reception INTCBnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CBnTX register INTCBnR interrupt generated? (8) Yes No (9) CBnOVE bit = 1? (CBnSTR) (10) Yes (13) (13) Re
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 07H to the CBnCTL1 re
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (12) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, the INTCBnR signal is generated. Clear the CBnTSF bit to 0 to end transmission/reception. (13) When the INTCBnR signal is generated, read the CBnRX register. (14) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.13 Reception error When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCBnR) is generated again when the next receive operation is completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is set to 1.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.14 Clock timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit (ii) Communication type 3 (CBnCKP and CBnDAP bits = 10) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit Notes 1.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin SIBn capture D7 SOBn pin D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit (iv) Communication type 4 (CBnCKP and CBnDAP bits = 11) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit Notes 1.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.7 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 0 1 1 1 Other than above 1 1 1 High impedance Fixed to high level 1 Other than above SCKBn Pin Output High impedance Fixed to low level Remarks 1. The output level of the SCKBn pin changes if any of the CBnCTL1.CBnCKP and CBnCKS2 to CBnCKS0 bits is rewritten. 2.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.8 Baud Rate Generator The BRG1 to BRG3 and CSIB0 to CSIB4 baud rate generators are connected as shown in the following block diagram. fX fBRG1 BRG1 CSIB0 CSIB1 fX fBRG2 BRG2 CSIB2 CSIB3 fX fBRG3 BRG3 CSIB4 (1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIB. These registers can be read or written in 8-bit or 1-bit units.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H PRSCMm (m = 1 to 3) PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0 Cautions 1. Do not rewrite the PRSCMm register during operation.
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V850ES/JG3 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed. (2) In regards to registers that are forbidden from being rewritten during operations (CBnCTL0.
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CHAPTER 17 I2C BUS V850ES/JG3 CHAPTER 17 I2C BUS To use the I2C bus function, use the P38/SDA00, P39/SCL00, P40/SDA01, P41/SCL01, P90/SDA02, and P91/SCL02 pins as the serial transmit/receive data I/O pins (SDA00 to SDA02) and serial clock I/O pins (SCL00 to SCL02), respectively, and set them to N-ch open-drain output. 17.1 Mode Switching of I2C Bus and Other Serial Interfaces 17.1.
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CHAPTER 17 I2C BUS V850ES/JG3 2 17.1.2 CSIB0 and I C01 mode switching In the V850ES/JG3, CSIB0 and I2C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I2C01 in advance, using the PMC4 and PFC4 registers, before use. Caution The transmit/receive operation of CSIB0 and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-2.
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CHAPTER 17 I2C BUS V850ES/JG3 2 17.1.3 UARTA1 and I C02 mode switching In the V850ES/JG3, UARTA1 and I2C02 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I2C02 in advance, using the PMC9, PFC9, and PMCE9 registers, before use. Caution The transmit/receive operation of UARTA1 and I2C02 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-3.
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CHAPTER 17 I2C BUS V850ES/JG3 17.2 Features I2C00 to I2C02 have the following two modes. • Operation stopped mode • I2C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) I2C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a serial data bus pin (SDA0n).
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CHAPTER 17 I2C BUS V850ES/JG3 17.3 Configuration The block diagram of the I2C0n is shown below. Figure 17-4.
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CHAPTER 17 I2C BUS V850ES/JG3 A serial bus configuration example is shown below. Figure 17-5. Serial Bus Configuration Example Using I2C Bus +VDD +VDD Master CPU1 SDA Slave CPU1 Address 1 R01UH0015EJ0300 Rev.3.
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CHAPTER 17 I2C BUS V850ES/JG3 2 I C0n includes the following hardware (n = 0 to 2). Table 17-1.
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CHAPTER 17 I2C BUS V850ES/JG3 (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I2C interrupt is generated following either of two triggers. • Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) • Interrupt occurrence due to stop condition detection (set by IICCn.
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V850ES/JG3 CHAPTER 17 I2C BUS 17.4 Registers I2C00 to I2C02 are controlled by the following registers. • IIC control registers 0 to 2 (IICC0 to IICC2) • IIC status registers 0 to 2 (IICS0 to IICS2) • IIC flag registers 0 to 2 (IICF0 to IICF2) • IIC clock select registers 0 to 2 (IICCL0 to IICCL2) • IIC function expansion registers 0 to 2 (IICX0 to IICX2) • IIC division clock select registers 0, 1 (OCKS0, OCKS1) The following registers are also used.
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CHAPTER 17 I2C BUS V850ES/JG3 (1/4) After reset: 00H IICCn R/W Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H <7> <6> <5> <4> <3> <2> <1> <0> IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0 to 2) 2 IICEn Specification of I Cn operation enable/disable Note 1 0 Operation stopped. IICSn register reset 1 Operation enabled. . Internal operation stopped. Be sure to set this bit to 1 when the SCL0n and SDA0n lines are high level.
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CHAPTER 17 I2C BUS V850ES/JG3 (2/4) Note SPIEn Enable/disable generation of interrupt request when stop condition is detected 0 Disabled 1 Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) • Cleared by instruction • Set by instruction • After reset Note WTIMn Control of wait state and interrupt request generation 0 Interrupt request is generated at the eighth clock’s falling edge.
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CHAPTER 17 I2C BUS V850ES/JG3 (3/4) STTn Start condition trigger 0 Start condition is not generated. 1 When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCL0n line is high level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0n line is changed to low level.
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CHAPTER 17 I2C BUS V850ES/JG3 (4/4) SPTn Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed from low level to high level and a stop condition is generated.
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CHAPTER 17 I2C BUS V850ES/JG3 (2) IIC status registers 0 to 2 (IICS0 to IICS2) The IICSn register indicates the status of the I2C0n (n = 0 to 2). This register is read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn bit is 1 or during the wait period. Reset sets this register to 00H. Caution Accessing the IICSn register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
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CHAPTER 17 I2C BUS V850ES/JG3 (2/3) COIn Matching address detection 0 Addresses do not match. 1 Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) • When a start condition is detected • When the received address matches the local • When a stop condition is detected address (SVAn register) (set at the rising edge of the • Cleared by LRELn bit = 1 (communication save) eighth clock).
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CHAPTER 17 I2C BUS V850ES/JG3 (3/3) STDn Start condition detection 0 Start condition was not detected. 1 Start condition was detected.
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V850ES/JG3 CHAPTER 17 I2C BUS (3) IIC flag registers 0 to 2 (IICF0 to IICF2) The IICFn register sets the I2C0n operation mode and indicates the I2C bus status. This register can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only. IICRSVn enables/disables the communication reservation function (see 17.14 Communication Reservation). The initial value of the IICBSYn bit is set by using the STCENn bit (see 17.15 Cautions).
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CHAPTER 17 I2C BUS V850ES/JG3 After reset: 00H IICFn R/W Note Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH, IICF2 FFFFFDAAH <7> <6> 5 4 3 2 <1> <0> STCFn IICBSYn 0 0 0 0 STCENn IICRSVn (n = 0 to 2) STCFn STTn bit clear 0 Start condition issued 1 Start condition cannot be issued, STTn bit cleared Condition for clearing (STCFn bit = 0) Condition for setting (STCFn bit = 1) • Cleared by IICCn.
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CHAPTER 17 I2C BUS V850ES/JG3 (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) The IICCLn register sets the transfer clock for the I2C0n. This register can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Set the IICCLn register when the IICCn.IICEn bit = 0. The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn bit and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.
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CHAPTER 17 I2C BUS V850ES/JG3 (5) IIC function expansion registers 0 to 2 (IICX0 to IICX2) The IICXn register sets I2C0n function expansion (valid only in the high-speed mode). This register can be read or written in 8-bit or 1-bit units. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.4 (6) I2C0n transfer clock setting method) (m = 0, 1).
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CHAPTER 17 I2C BUS V850ES/JG3 Table 17-2. Clock Settings (1/2) IICX0 IICCL0 Selection Clock Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 0 0 0 0 0 0 0 1 Transfer Settable Main Clock Operating Clock Frequency (fXX) Range Mode fXX (when OCKS0 = 18H set) fXX/44 2.00 MHz ≤ fXX ≤ 4.19 MHz Standard mode fXX/2 (when OCKS0 = 10H set) fXX/88 4.00 MHz ≤ fXX ≤ 8.38 MHz (SMC0 bit = 0) fXX/3 (when OCKS0 = 11H set) fXX/132 6.00 MHz ≤ fXX ≤ 12.
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CHAPTER 17 I2C BUS V850ES/JG3 Table 17-2. Clock Settings (2/2) IICXm Bit 0 IICCLm Bit 3 Bit 1 CLXm SMCm CLm1 0 0 0 0 Selection Clock Bit 0 Transfer Settable Main Clock Operating Clock Frequency (fXX) Range Mode CLm0 0 0 0 1 fXX (when OCKS1 = 18H set) fXX/44 2.00 MHz ≤ fXX ≤ 4.19 MHz Standard fXX/2 (when OCKS1 = 10H set) fXX/88 4.00 MHz ≤ fXX ≤ 8.38 MHz mode fXX/3 (when OCKS1 = 11H set) fXX/132 6.00 MHz ≤ fXX ≤ 12.57 MHz fXX/4 (when OCKS1 = 12H set) fXX/176 8.
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CHAPTER 17 I2C BUS V850ES/JG3 (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKSm register controls the I2C0n division clock (n = 0 to 2, m = 0, 1). This register controls the I2C00 division clock via the OCKS0 register and the I2C01 and I2C02 division clocks via the OCKS1 register. This register can be read or written in 8-bit units. Reset sets this register to 00H.
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CHAPTER 17 I2C BUS V850ES/JG3 (9) Slave address registers 0 to 2 (SVA0 to SVA2) The SVAn register holds the I2C bus’s slave addresses (n = 0 to 2). This register can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting this register is prohibited when the IICSn.STDn bit = 1 (start condition detection). Reset sets this register to 00H.
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CHAPTER 17 I2C BUS V850ES/JG3 17.5 I2C Bus Mode Functions 17.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2). SCL0n .................This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0n ................This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices.
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CHAPTER 17 I2C BUS V850ES/JG3 17.6 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus. The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition” generated on the I2C bus’s serial data bus is shown below. Figure 17-7.
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CHAPTER 17 I2C BUS V850ES/JG3 17.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
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CHAPTER 17 I2C BUS V850ES/JG3 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 17-10.
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CHAPTER 17 I2C BUS V850ES/JG3 17.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed with the IICSn.ACKDn bit.
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CHAPTER 17 I2C BUS V850ES/JG3 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0 to 2). A stop condition is generated when serial transfer from the master device to the slave device has been completed. When used as the slave device, the start condition can be detected. Figure 17-12. Stop Condition H SCL0n SDA0n Remark n = 0 to 2 A stop condition is generated when the IICCn.SPTn bit is set to 1.
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CHAPTER 17 I2C BUS V850ES/JG3 17.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2). Figure 17-13.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-13. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait after output of ninth clock. IICn data write (cancel wait state) Master IICn 6 SCL0n 7 8 1 9 2 3 Slave FFH is written to IICn register or WRELn bit is set to 1.
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V850ES/JG3 CHAPTER 17 I2C BUS 17.6.7 Wait state cancellation method In the case of I2C0n, wait state can be canceled normally in the following ways (n = 0 to 2). • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait state cancellation) • By setting the IICCn.STTn bit to 1 (start condition generation) • By setting the IICCn.
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CHAPTER 17 I2C BUS V850ES/JG3 17.7 I2C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing (n = 0 to 2). 17.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICCn.WTIMn bit = 0 IICCn.
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CHAPTER 17 I2C BUS V850ES/JG3 (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 STTn bit = 1 SPTn bit = 1 ↓ ↓ ACK S2 ST AD6 to AD0 R/W ACK S3 D7 to D0 S4 ACK S5 SP S6 Δ7 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B (WTIMn bit = 0) S4: IICSn register = 1000X110B (WTIMn bit = 0) S5: IICSn register = 1000X000B (WTIMn bit = 1) S6: IICSn register = 100
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CHAPTER 17 I2C BUS V850ES/JG3 (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK S3 SP S4 Δ5 S1: IICSn register = 1010X110B S2: IICSn register = 1010X000B S3: IICSn register = 1010X000B (WTIMn bit = 1) S4: IICSn register = 1010XX00B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 17.7.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP Δ4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X000B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP Δ4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 00000X10B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 17.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP Δ4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP Δ5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B Δ 5: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP Δ4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 00000X10B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 17.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 2. n = 0 to 2 17.7.5 Arbitration loss operation (operation as slave after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data <1> When IICCn.
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CHAPTER 17 I2C BUS V850ES/JG3 (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP Δ4 S3 S1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B Δ 4: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP Δ2 S1 S1: IICSn register = 01000110B (Example: When IICSn.ALDn bit is read during interrupt servicing) Δ 2: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when IICCn.SPIEn bit = 1 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 ACK SP Δ3 S2 S1: IICSn register = 10001110B S2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) Δ 3: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK SP Δ3 S2 S1: IICSn register = 1000X110B S2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ 3: IICSn register = 00000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (5) When arbitration loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn S1 SP Δ2 S1: IICSn register = 1000X110B Δ 2: IICSn register = 01000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. Dn = D6 to D0 n = 0 to 2 R01UH0015EJ0300 Rev.3.
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CHAPTER 17 I2C BUS V850ES/JG3 (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.
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CHAPTER 17 I2C BUS V850ES/JG3 (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 SP Δ4 S3 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B Δ 4: IICSn register = 01000001B Remarks 1. S: Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2.
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CHAPTER 17 I2C BUS V850ES/JG3 (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.
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CHAPTER 17 I2C BUS V850ES/JG3 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below (n = 0 to 2). Table 17-3. INTIICn Generation Timing and Wait Control WTIMn Bit During Slave Device Operation Address 0 1 Notes 1.
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CHAPTER 17 I2C BUS V850ES/JG3 (4) Wait state cancellation method The four wait state cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • By start condition setting (IICCn.STTn bit = 1)Note • By stop condition setting (IICCn.SPTn bit = 1)Note Note Master only When an 8-clock wait has been selected (WTIMn bit = 0), whether or not ACK has been generated must be determined prior to wait cancellation.
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CHAPTER 17 I2C BUS V850ES/JG3 17.9 Address Match Detection Method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2). 17.
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CHAPTER 17 I2C BUS V850ES/JG3 17.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2). When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.
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CHAPTER 17 I2C BUS V850ES/JG3 Table 17-5.
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V850ES/JG3 CHAPTER 17 I2C BUS 17.14 Communication Reservation 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
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CHAPTER 17 I2C BUS V850ES/JG3 Table 17-6.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-15. Communication Reservation Timing Program processing Hardware processing SCL0n 1 2 3 4 STTn =1 Write to IICn Set SPDn and INTIICn Communication reservation 5 6 7 8 9 Set STDn 1 2 3 4 5 6 SDA0n Generated by master with bus access Remark n = 0 to 2 STTn: Bit of IICCn register STDn: Bit of IICSn register SPDn: Bit of IICSn register Communication reservations are accepted via the following timing. After the IICSn.
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CHAPTER 17 I2C BUS V850ES/JG3 The communication reservation flowchart is illustrated below. Figure 17-17. Communication Reservation Flowchart DI SET1 STTn Define communication reservation Wait Sets STTn bit (communication reservation). Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 17-6).
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CHAPTER 17 I2C BUS V850ES/JG3 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used.
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CHAPTER 17 I2C BUS V850ES/JG3 17.15 Cautions (1) When IICFn.STCENn bit = 0 Immediately after the I2C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. Use the following sequence for generating a stop condition. <1> Set the IICCLn register.
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CHAPTER 17 I2C BUS V850ES/JG3 17.16 Communication Operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the V850ES/JG3 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
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CHAPTER 17 I2C BUS V850ES/JG3 17.16.1 Master operation in single master system Figure 17-18. Master Operation in Single Master System START Initialize I2C busNote Set ports Initial settings IICXn ← 0XH IICCLn ← XXH OCKSm ← XXH Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used.
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CHAPTER 17 I2C BUS V850ES/JG3 17.16.2 Master operation in multimaster system Figure 17-19. Master Operation in Multimaster System (1/3) START Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-19.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-19.
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CHAPTER 17 I2C BUS V850ES/JG3 17.16.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary. The following description assumes that data communication does not support extension codes.
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CHAPTER 17 I2C BUS V850ES/JG3 For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications. Figure 17-21. Slave Operation Flowchart (1) START Refer to Table 4-15 Using Port Pin as Alternate-Function Pins to set the I2C mode before this function is used.
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CHAPTER 17 I2C BUS V850ES/JG3 The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated.
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V850ES/JG3 CHAPTER 17 I2C BUS 17.17 Timing of Data Communication When using I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-23.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-23.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-23.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-24.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-24.
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CHAPTER 17 I2C BUS V850ES/JG3 Figure 17-24.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) The V850ES/JG3 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL. These registers can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (3) DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer. These registers are decremented by 1 per one transfer regardless of the transfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. These registers can be read or written in 16-bit units.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units. Reset sets these registers to 0000H.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are writeonly. If bit 1 or 2 is read, the read value is always 0.) Reset sets these registers to 00H.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units. Reset sets these registers to 00H.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-1.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-1. DMA Start Factors (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 1 0 1 0 1 1 INTUA2T 1 0 1 1 0 0 INTAD 1 0 1 1 0 1 INTKR Other than above Remark Interrupt Source Setting prohibited n = 0 to 3 18.4 Transfer Targets Table 18-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled). Table 18-2.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.5 Transfer Modes Single transfer is supported as the transfer mode. In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle. 18.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3).
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.10 DMA Abort Factors DMA transfer is aborted if a bus hold occurs. The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/onchip peripheral I/O. When the bus hold is cleared, DMA transfer is resumed. 18.11 End of DMA Transfer When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.
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V850ES/JG3 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 18-1. Priority of DMA (1) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation for transfer Read Write End processing Preparation for transfer Read Idle Mode of processing CPU processing DMA0 processing Write End processing Preparation for transfer Read Idle CPU processing Remarks 1. Transfer in the order of DMA0 → DMA1 → DMA2 2.
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V850ES/JG3 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 18-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation for transfer Read Write End processing Preparation for transfer Idle Mode of processing CPU processing DMA0 processing Read Write End processing Preparation for transfer Read Idle CPU processing Remarks 1. Transfer in the order of DMA0 → DMA1 → DMA0 (DMA2 is held pending.) 2.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Figure 18-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer requestNote 1 DFn bit Mode of processing Note 2 CPU processing DMA transfer Preparation for transfer Note 2 Note 2 DMA0 processing Read cycle Write cycle CPU processing End processing Idle Transfer request generated after this can be acknowledged Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit) 2.
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V850ES/JG3 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 18-4.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System wait control register (VSWC)).
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized. To accurately initialize the channel, execute either of the following two procedures. (a) Temporarily stop transfer of all DMA channels Initialize the channel executing DMA transfer using the procedure in <1> to <7> below.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by using the DTFRn.DFn bit.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (8) Bus arbitration for CPU Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU. However, the CPU can access the internal ROM, and internal RAM to/from which DMA transfer is not being executed.
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V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (12) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/JG3 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 57 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The priority order of non-maskable interrupt is INTWDT2 > NMI. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. This product has the following two non-maskable interrupt request signals.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-1.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the PSW.NP bit is 1. <2> Transfers control back to the address of the restored PC and PSW.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 19-4. Software Reset Processing INTWDT2 occurs. FEPC ← Software reset processing address FEPSW ← Value that sets NP bit = 1, EP bit = 0 INTWDT2 servicing routine ↓ RETI RETI 10 times (FEPC and FEPSWNote must be set.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JG3 has 55 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-5.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW, respectively, because the PSW.EP bit is 0 and the PSW.NP bit is 0. <2> Transfers control back to the address of the restored PC and PSW.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Servicing of b EI Interrupt request b (level 2) Interrupt request a (level 3) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI Servicing of k EI Interrupt request j (level 3) Interrupt request k (level 1) Interrupt request i (level 2) Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Default priority a>b>c Servicing of interrupt request b Servicing of interrupt request c . . Interrupt request b and c are acknowledged first according to their priorities.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H. Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH 15 Note IMR3 (IMR3H ) IMR3L R/W 14 ) 12 11 10 9 8 1 1 1 0 1 1 1 1 1 7 6 5 4 3 2 1 WTMK WTIMK KRMK R/W DMAMK3 DMAMK2 DMAMK1 DMAMK0 Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H 14 13 12 11 10 9 8 ADMK UA2TMK UA2RMK/ IICMK0 UA1TMK UA1RMK/ IIC2MK UA0TMK/ CB4TMK UA0RMK/ CB4RMK CB3TMK 7 6 5 4 3 2 1 0 CB0RMK/ IICMK1 TM0EQMK0 15 IMR2 (IMR2H 13 1 After reset: F
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.7 ID flag This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 19.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the PSW.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.2 Restore Restoration from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 19-10.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H PSW 0 EP NP ID SAT CY OV S Z Exception processing status 0 Exception processing not in progress. 1 Exception processing in progress. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/JG3, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 19.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing. <1> Saves restored PC to DBPC. <2> Saves current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets handler address (00000060H) for debug trap to PC and transfers control.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2> Control is transferred to the fetched address of the restored PC and PSW.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) 19.6.1 Noise elimination (1) Eliminating noise on NMI pin The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. The NMI pin can be used to release the STOP mode.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP7). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Cautions 1.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP4 to INTP6). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Noise elimination control register (NFC) Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed three times.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. • In IDLE1/IDLE2/STOP mode • When the external bus is accessed • When interrupt request non-sampling instructions are successively executed (see 19.
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V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
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V850ES/JG3 CHAPTER 20 KEY INTERRUPT FUNCTION CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Table 20-1.
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V850ES/JG3 CHAPTER 20 KEY INTERRUPT FUNCTION 20.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION CHAPTER 21 STANDBY FUNCTION 21.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 21-1. Table 21-1.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION Figure 21-1.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register. The OSTS register can be read or written 8-bit units. Reset sets this register to 06H.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.3 HALT Mode 21.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 21-3.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.4 IDLE1 Mode 21.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was set are retained.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION Table 21-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Non-maskable interrupt request Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed. or the next instruction is executed.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.5 IDLE2 Mode 21.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are retained.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION Table 21-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address after securing the prescribed setup time. Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed after securing the prescribed setup time.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register.
PAGE 701
V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.6 STOP Mode 21.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION Table 21-8. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address after securing the oscillation stabilization time. Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time.
PAGE 703
V850ES/JG3 CHAPTER 21 STANDBY FUNCTION (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. Table 21-9.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.6.3 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.7 Subclock Operation Mode 21.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. Check whether the clock has been switched by using the PCC.CLS bit. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION Table 21-10.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION 21.8 Sub-IDLE Mode 21.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on-chip peripheral functions is stopped.
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V850ES/JG3 CHAPTER 21 STANDBY FUNCTION Table 21-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Non-maskable interrupt request Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed. or the next instruction is executed.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS CHAPTER 22 RESET FUNCTIONS 22.1 Overview The following reset functions are available.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS 22.2 Registers to Check Reset Source The V850ES/JG3 has four kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF). (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.7 Special registers). The RESF register indicates the source from which a reset signal is generated.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS 22.3 Operation 22.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. Table 22-1.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS Figure 22-2. Timing of Reset Operation by RESET Pin Input fX fCLK Initialized to fXX/8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 22-3.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS 22.3.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS Figure 22-4. Timing of Reset Operation by WDT2RES Signal Generation fX fCLK Initialized to fXX/8 operation WDT2RES Analog delay Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflow R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS 22.3.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status. The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI detection voltage.
PAGE 716
V850ES/JG3 CHAPTER 22 RESET FUNCTIONS 22.3.4 Operation after reset release After the reset is released, the main clock starts oscillation and oscillation stabilization time (OSTS register initial value: 216/fX) is secured, and the CPU starts program execution. WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source clock. Figure 22-5.
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V850ES/JG3 CHAPTER 22 RESET FUNCTIONS 22.3.5 Reset function operation flow Start (reset source occurs) Set RESF registerNote 1 Reset occurs → reset release Internal oscillation and main clock oscillation start, WDT2 count up starts (reset mode) Main clock oscillation stabilization time secured? No Yes (in normal operation mode) No WDT2 overflow? Yes (in emergent operation mode) fCPU = fRNote 2 CCLS.
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V850ES/JG3 CHAPTER 23 CLOCK MONITOR CHAPTER 23 CLOCK MONITOR 23.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 22.
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V850ES/JG3 CHAPTER 23 CLOCK MONITOR 23.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.7 Special registers). This register is used to set the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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V850ES/JG3 CHAPTER 23 CLOCK MONITOR 23.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. Enabling operation by setting the CLM.CLME bit to 1 • While oscillation stabilization time is being counted after STOP mode is released • When the main clock is stopped (from when PCC.MCK bit = 1 during subclock operation to when PCC.
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V850ES/JG3 CHAPTER 23 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in Figure 23-2. Figure 23-2. Reset Period Due to That Oscillation of Main Clock Is Stopped Four internal oscillation clocks Main clock Internal oscillation clock Internal reset signal CLM.CLME bit RESF.CLMRF bit (2) Clock monitor status after RESET input RESET input clears the CLM.
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V850ES/JG3 CHAPTER 23 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started. Figure 23-4.
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V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.1 Functions The low-voltage detector (LVI) has the following functions. • If the interrupt occurrence at low voltage detection is selected, the low-voltage detector continuously compares the supply voltage (VDD) and the detected voltage (VLVI), and generates an internal interrupt signal when the supply voltage drops or rises across the detected voltage.
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V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.3 Registers The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level select register (LVIS) • Internal RAM data status register (RAMS) (1) Low-voltage detection register (LVIM) The LVIM register is a special register. This can be written only in the special combination of the sequences (see 3.4.7 Special registers).
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V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) (2) Low-voltage detection level select register (LVIS) The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit or 1-bit units. After reset: Note LVIS R/W Address: FFFFF891H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LVIS0 LVIS0 Detection level 0 2.95 V (TYP.) ±0.
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V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 24.4.1 To use for internal reset signal <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit. <3> Set the LVIM.LVION bit to 1 (to enable operation). <4> Insert a wait cycle of 0.
PAGE 727
V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4.2 To use for interrupt <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit. <3> Set the LVIM.LVION bit to 1 (to enable operation). <4> Insert a wait cycle of 0.2 ms (max.) or more by software. <5> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage. <6> Clear the interrupt request flag of LVI. <7> Unmask the interrupt of LVI.
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V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.5 RAM Retention Voltage Detection Operation The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage (including on power application), the RAMS.RAMF bit is set to 1. Figure 24-4. Operation Timing of RAM Retention Voltage Detection Function Initialize RAM (RAMF bit is also cleared) VDD < 2.0 V detected Set RAMF bit Initialize RAM (RAMF bit is also cleared) Supply voltage (VDD) 2.
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V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.6 Emulation Function When an in-circuit emulator is used, the operation of the RAM retention flag (RAMS.RAMF bit) can be pseudocontrolled and emulated by manipulating the PEMU1 register on the debugger. This register is valid only in the emulation mode. It is invalid in the normal mode.
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V850ES/JG3 CHAPTER 25 CRC FUNCTION CHAPTER 25 CRC FUNCTION 25.1 Functions • CRC operation circuit for detection of data block errors • Generation of 16-bit CRC code using a CRC-CCITT (X16 + X12 + X5 + 1) generation polynomial for blocks of data of any length in 8-bit units • CRC code is set to the CRC data register each time 1-byte data is transferred to the CRCIN register, after the initial value is set to the CRCD register. 25.2 Configuration The CRC function includes the following hardware.
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V850ES/JG3 CHAPTER 25 CRC FUNCTION 25.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF310H 6 7 5 4 3 2 1 0 CRCIN (2) CRC data register (CRCD) The CRCD register is a 16-bit register that stores the CRC-CCITT operation results. This register can be read or written in 16-bit units. Reset sets this register to 0000H.
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V850ES/JG3 CHAPTER 25 CRC FUNCTION 25.4 Operation An example of the CRC operation circuit is shown below. Figure 25-2. CRC Operation Circuit Operation Example (LSB First) b7 b0 (1) Setting of CRCIN = 01H b15 b0 (2) CRCD register read 1189H CRC code is stored The code when 01H is sent LSB first is (1000 0000). Therefore, the CRC code from generation polynomial X16 + X12 + 5 X + 1 becomes the remainder when (1000 0000) X16 is divided by (1 0001 0000 0010 0001) using the modulo-2 operation formula.
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V850ES/JG3 CHAPTER 25 CRC FUNCTION 25.5 Usage Method How to use the CRC logic circuit is described below. Figure 25-3. CRC Operation Flow Start Write of 0000H to CRCD register Input data exists? Yes No CRCD register read CRCIN register write End [Basic usage method] <1> Write 0000H to the CRCD register. <2> Write the required quantity of data to the CRCIN register. <3> Read the CRCD register. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 25 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example. Figure 25-4.
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V850ES/JG3 CHAPTER 26 REGULATOR CHAPTER 26 REGULATOR 26.1 Overview The V850ES/JG3 includes a regulator to reduce power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers). The regulator output voltage is set to 2.5 V (TYP.). Figure 26-1.
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V850ES/JG3 CHAPTER 26 REGULATOR 26.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, or during reset). Be sure to connect a capacitor (4.7 μF (recommended value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below. Figure 26-2. REGC Pin Connection Voltage supply to sub-oscillator VDD Input voltage = 2.85 to 3.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY CHAPTER 27 FLASH MEMORY The V850ES/JG3 incorporates a flash memory. • μPD70F3739: 384 KB flash memory • μPD70F3740: 512 KB flash memory • μPD70F3741: 768 KB flash memory • μPD70F3742: 1024 KB flash memory Flash memory versions offer the following advantages for development environments and mass production applications. For altering software after the V850ES/JG3 is soldered onto the target system. For data adjustment when starting mass production.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.2 Memory Configuration The V850ES/JG3 internal flash memory area is divided into 4 KB blocks and can be programmed/erased in block units. All or some of the blocks can also be erased at once. When the boot swap function is used, the physical memory allocated at the addresses of blocks 0 to 15 is replaced by the physical memory allocated at the addresses of blocks 16 to 31. For details of the boot swap function, see 27.5 Rewriting by Self Programming.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Figure 27-1.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.3 Functional Outline The internal flash memory of the V850ES/JG3 can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/JG3 has already been mounted on the target system or not (off-board/onboard programming). In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Table 27-2. Basic Functions Function Support (√: Supported, ×: Not supported) Functional Outline On-Board/Off-Board Self Programming Programming Blank check The erasure status of the entire memory is √ √ checked. Chip erasure The contents of the entire memory area √ × Note are erased all at once. Block erasure The contents of specified memory blocks √ √ √ √ are erased.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Table 27-4.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/JG3 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 27.4.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/JG3 is performed by serial communication using the UARTA0, CSIB0, or CSIB3 interfaces of the V850ES/JG3. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 27-3.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY (3) CSIB0 + HS, CSIB3 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 27-5. Communication with Dedicated Flash Programmer (CSIB0 + HS, CSIB3 + HS) FLMD0 FLMD0 FLMD1 FLMD1Note VDD VDD GND VSS RESET Dedicated flash programmer RESET SI SOB0, SOB3 SO V850ES/JG3 SIB0, SIB3 SCK SCKB0, SCKB3 HS PCM0 Note Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-down resistor on the board.
PAGE 746
V850ES/JG3 CHAPTER 27 FLASH MEMORY Table 27-6. Wiring of Flash Writing Adapter for V850ES/JG3 (FA-100GC-8EU-A) (1/2) Flash Programmer (PG-FP4) Connection Pins Signal I/O Pin Name on FA Board Pin Function When CSIB0 + HS Is Used Pin Name Name SI/RxD When CSIB0 Is Used Pin Pin Name No. Input Receive signal SO/TxD Output Transmit signal When UARTA0 Is Used Pin Pin Name No. Pin No.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Table 27-6. Wiring of Flash Writing Adapter for V850ES/JG3 (FA-100GC-8EU-A) (2/2) Flash Programmer (PG-FP4) Connection Pins Signal I/O Pin Name on FA Board When CSIB3 + HS Is Used Pin Function Pin Name Name SI/RxD When CSIB3 Is Used Pin Pin Name Pin No. Input Receive signal No.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Figure 27-6. Example of Wiring of V850ES/JG3 Flash Writing Adapter (FA-100GC-8EU-A) (in CSIB0 + HS Mode) (1/2) G D D VD D VD ND N G 75 76 70 65 60 55 51 Note 2 50 Note 1 80 45 85 40 V850ES/JG3 90 35 95 Connect this pin to GND. 30 Connect this pin to VDD. e 4 4.7 μ F (recommended value) 5 10 N Note 3 1 26 ot 100 15 20 25 G D N N D VD D G SI R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Figure 27-6. Example of Wiring of V850ES/JG3 Flash Writing Adapter (FA-100GC-8EU-A) (in CSIB0 + HS Mode) (2/2) Notes 1. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 2. Pins used when CSIB3 is used 3. Supply a clock by creating an oscillator on the flash writing adapter (enclosed by the broken lines). Here is an example of the oscillator. Example X1 X2 4. Pins used when UARTA0 is used.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 27-7. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode Supplies FLMD0 pulse Select communication system Manipulate flash memory End? No Yes End R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.4.4 Selection of communication mode In the V850ES/JG3, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 27-8.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.4.5 Communication commands The V850ES/JG3 communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/JG3 are called “commands”. The response signals sent from the V850ES/JG3 to the dedicated flash programmer are called “response commands”. Figure 27-9.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY Table 27-8. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 FLMD1 0 Don’t care VDD 0 VDD VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited (3) Serial interface pin The following shows the pins used by each serial interface. Table 27-9.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 27-13.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.5 Rewriting by Self Programming 27.5.1 Overview The V850ES/JG3 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.5.2 Features (1) Secure self programming (boot swap function) The V850ES/JG3 supports a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 27-17.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.5.4 Flash functions Table 27-10.
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V850ES/JG3 CHAPTER 27 FLASH MEMORY 27.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 27-11. Internal Resources Used Resource Name Stack area Note Description An extension of the stack used by the user is used by the library (can be used in both the internal RAM and external RAM).
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION CHAPTER 28 ON-CHIP DEBUG FUNCTION The V850ES/JG3 on-chip debug function can be implemented by the following two methods. • Using the DCU (debug control unit) On-chip debug function is implemented by the on-chip DCU in the V850ES/JG3, with using the DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins. • Not using the DCU On-chip debug function is implemented by MINICUBE2 or the like, using the user resources, instead of the DCU.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.1 Debugging with DCU Programs can be debugged using the debug interface pins (DRST, DCK, DMS, DDI, and DDO) to connect the on-chip debug emulator (MINICUBE). 28.1.1 Connection circuit example Figure 28-1.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION (2) DCK This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge. (3) DMS This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of the DMS signal. (4) DDI This is a data input signal.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.1.3 Maskable functions Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JG3 functions are listed below. Table 28-2.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION After reset: 01HNote R/W Address: FFFFF9FCH < > OCDM 0 0 0 0 OCDM0 0 0 0 0 OCDM0 Operation mode Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P05/INTP2/DRST pin.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.1.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0. OCDM0 Flag 0 1 L Invalid Invalid H Invalid Valid DRST Pin Remark L: Low-level input H: High-level input Figure 28-2.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.2 Debugging Without Using DCU The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTA0 (RXDA0 and TXDA0), pins for CSIB0 (SIB0, SOB0, SCKB0, and HS (PCM0)), or pins for CSIB3 (SIB3, SOB3, SCKB3, and HS (PCM0)) as debug interfaces, without using the DCU. 28.2.1 Circuit connection examples Figure 28-3.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION Table 28-3. Wiring Between V850ES/JG3 and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) Signal Name I/O Pin Function With CSIB0-HS Pin Name With CSIB3-HS Pin Pin Name Pin With UARTA0 Pin Name Pin No. No. No.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.2.3 Securement of user resources The user must prepare the following to perform communication between MINICUBE2 and the target device and implement each debug function. These items need to be set in the user program or using the compiler options. (1) Securement of memory space The shaded portions in Figure 28-4 are the areas reserved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION Figure 28-4. Memory Spaces Where Debug Monitor Programs Are Allocated Internal RAM Internal ROM 3FFEFFFH 3FFEFF0H (16 bytes) (2 KB) Note 1 Internal RAM area Note 3 0000290H Note 2 CSI0/UART receive interrupt vector (4 bytes) Access-prohibited area Internal ROM area 0000070H Security ID area (10 bytes) 0000060H Interrupt vector for debugging (4 bytes) 0000000H Reset vector (4 bytes) : Debugging area Notes 1.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION (3) Reset vector A reset vector includes the jump instruction for the debug monitor program. [How to secure areas] It is not necessary to secure this area intentionally. When downloading a program, however, the debugger rewrites the reset vector in accordance with the following cases. If the rewritten pattern does not match the following cases, the debugger generates an error (F0C34 when using the ID850QB).
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION (4) Securement of area for debug monitor program The shaded portions in Figure 28-4 are the areas where the debug monitor program is allocated. The monitor program performs initialization processing for debug communication interface and RUN or break processing for the CPU. The internal ROM area must be filled with 0xFF. This area must not be rewritten by the user program.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION (5) Securement of communication serial interface UARTA0, CSIB0, or CSIB3 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur. To prevent such a problem from occurring, communication serial interface must be secured in the user program.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION • Port registers when UARTA0 is used When UARTA0 is used, port registers are set to make the TXDA0 and RXDA0 pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION • Port registers when CSIB3 is used When CSIB3 is used, port registers are set to make the SIB3, SOB3, SCKB3, and HS (PMC0) pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION (3) When pseudo real-time RAM monitor (RRM) function and DMM function do not operate The pseudo RRM function and DMM function do not operate if one of the following conditions is satisfied.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.3 ROM Security Function 28.3.1 Security ID The flash memory versions of the V850ES/JG3 perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator. Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication.
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V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.3.2 Setting The following shows how to set the ID code as shown in Table 28-5. When the ID code is set as shown in Table 28-5, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4” (the ID code is case-insensitive). Table 28-5.
PAGE 780
V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION [Program example (when using CA850 Ver. 3.10 or later)] #-------------------------------------# SECURITYID #-------------------------------------.section “SECURITY_ID” --Interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Remark Add the above program example to the startup files. R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 29 CHAPTER 29 ELECTRICAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD VDD = EVDD = AVREF0 = AVREF1 −0.5 to +4.6 V EVDD VDD = EVDD = AVREF0 = AVREF1 −0.5 to +4.6 V AVREF0 VDD = EVDD = AVREF0 = AVREF1 −0.5 to +4.6 V AVREF1 VDD = EVDD = AVREF0 = AVREF1 −0.5 to +4.6 V VSS VSS = EVSS = AVSS −0.5 to +0.5 V AVSS VSS = EVSS = AVSS −0.5 to +0.
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V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Output current, low Symbol IOL Conditions Ratings Unit P02 to P06, P30 to P39, P40 to Per pin 4 mA P42, P50 to P55, P90 to P915, Total of all pins 50 mA PDH4, PDH5 PCM0 to PCM3, PCT0, PCT1, Per pin 4 mA PCT4, PCT6, PDH0 to PDH3, Total of all pins 50 mA Per pin 4 mA Total of all pins 8 mA Per pin 4 mA Total of all pins 20 mA P02 to P06, P30 to P39, P40 to Per pin −4 mA
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V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Capacitance (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1 = VSS = EVSS = AVSS = 0 V) Parameter I/O capacitance Symbol Conditions MIN. TYP. fX = 1 MHz CIO MAX. Unit 10 pF Unmeasured pins returned to 0 V Operating Conditions (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) Internal System Clock Conditions Frequency fXX = 2.5 to 32 MHz C = 4.
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V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Main Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) Resonator Circuit Example Parameter Ceramic Oscillation resonator/ frequency (fX) Conditions MIN. TYP. 2.5 MAX.
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V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (i) KYOCERA KINSEKI CORPORATION: Crystal resonator (TA = −10 to +70°C) Type Circuit Example Part Number Oscillation Recommended Circuit Constant Oscillation Voltage Frequency Surface X1 C1 C1 (pF) C2 (pF) Rd (Ω) MIN. (V) MAX. (V) CX49GFWB04000D0PESZZ 4.000 8 8 0 2.2 3.6 Rd CX49GFWB05000D0PESZZ 5.000 8 8 0 2.2 3.6 C2 CX49GFWB06000D0PESZZ 6.000 8 8 0 2.2 3.6 CX49GFWB08000D0PESZZ 8.000 8 8 0 2.2 3.
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V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Subclock Oscillator Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) Resonator Crystal Circuit Example XT1 XT2 Parameter Conditions Oscillation frequency MIN. TYP. MAX. Unit 32 32.768 35 kHz 10 s Note 1 (fXT) resonator Oscillation stabilization time Note 2 Notes 1. The oscillation frequency shown above indicates only oscillator characteristics.
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V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS PLL Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol Conditions fX fXX tPLL MIN. TYP. MAX. Unit ×4 mode 2.5 5 MHz ×8 mode 2.5 4 MHz ×4 mode 10 20 MHz ×8 mode 20 32 MHz 800 μs After VDD reaches 2.85 V (MIN.
PAGE 788
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) (1/3) Parameter Input voltage, high Symbol Conditions MIN. TYP. MAX. Unit VIH1 PDH4, PDH5 0.7EVDD EVDD V VIH2 RESET, FLMD0 0.8EVDD EVDD V VIH3 P02 to P06, P30 to P37, P42, P50 to P55, 0.8EVDD 5.5 V P92 to P915 VIH4 P38, P39, P40, P41, P90, P91 0.7EVDD 5.5 V VIH5 PCM0 to PCM3, PCT0, PCT1, PCT4, 0.
PAGE 789
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) (2/3) Parameter Output voltage, high Symbol VOH1 Conditions MIN. P02 to P06, Per pin Total of all pins P30 to P39, IOH = −1.0 mA −20 mA P40 to P42, Per pin Total of all pins P50 to P55, IOH = −100 μA −6.0 mA Per pin Total of all pins TYP. MAX. Unit EVDD − 1.0 EVDD V EVDD − 0.5 EVDD V EVDD − 1.0 EVDD V EVDD − 0.5 EVDD V AVREF0 − 1.
PAGE 790
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) (3/3) Parameter Supply current Note Symbol IDD1 IDD2 IDD3 Conditions Normal operation HALT mode IDLE1 mode MIN. TYP. MAX. Unit fXX = 32 MHz (fX = 4 MHz) 40 64 mA fXX = 20 MHz (fX = 5 MHz) 30 50 mA fXX = 32 MHz (fX = 4 MHz) 27 45 mA fXX = 20 MHz (fX = 5 MHz) 19 30 mA fXX = 5 MHz (fX = 5 MHz), 0.9 2.4 mA 0.3 0.
PAGE 791
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Data Retention Characteristics In STOP mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. 1.9 Data retention voltage VDDDR STOP mode (all functions stopped) Data retention current IDDDR STOP mode (all functions TYP. 8 MAX. Unit 3.6 V 80 μA stopped), VDDDR = 2.
PAGE 792
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points (VDD, AVREF0, AVREF1, EVDD) VDD VIH VIH Measurement points 0V VIL VIL AC Test Output Measurement Points VOH VOH Measurement points VOL VOL Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
PAGE 793
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS CLKOUT Output Timing (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. MAX. 31.25 μs Unit Output cycle tCYK <1> 31.25 ns High-level width tWKH <2> tCYK/2 − 6 ns Low-level width tWKL <3> tCYK/2 − 6 ns Rise time tKR <4> 6 ns Fall time tKF <5> 6 ns Clock Timing <1> <2> <3> CLKOUT (output) <4> R01UH0015EJ0300 Rev.3.
PAGE 794
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Bus Timing (1) In multiplexed bus mode Caution When operating at fXX > 20 MHz, be sure to insert address hold waits and address setup waits. (a) Read/write cycle (CLKOUT asynchronous) (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit <6> (0.5 + tASW)T − 20 tHSTA <7> (0.
PAGE 795
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A21 (output) <9> AD0 to AD15 (I/O) Hi-Z Address <6> Data <7> <12> ASTB (output) <17> <14> <8> <11> <10> <13> <15> RD (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark WR0 and WR1 are high level. R01UH0015EJ0300 Rev.3.
PAGE 796
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A21 (output) AD0 to AD15 (I/O) Address <6> ASTB (output) Data <7> <17> <18> <11> <14> <19> <20> WR0, WR1 (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark RD is high level. R01UH0015EJ0300 Rev.3.
PAGE 797
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 798
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A21 (output) <35> AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) WR0, WR1 (output) <32> <32> WAIT (input) <36> Remark <37> <36> <37> RD is high level. R01UH0015EJ0300 Rev.3.
PAGE 799
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) In separate bus mode Caution When operating at fXX > 20 MHz, be sure to insert address hold waits, address setup waits, and data waits. (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Address setup time (to RD↓) Symbol tSARD Conditions <38> Address hold time (from RD↑) tHARD <39> RD low-level width tWRDL <40> MIN. MAX. Unit (0.
PAGE 800
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Separate Bus Mode TW T1 T2 CLKOUT (output) A0 to A21 (output) <39> <43> AD0 to AD15 (I/O) Hi-Z Hi-Z <42> <38> <41> <40> RD (output) <47> <45> <46> <44> WAIT (input) <48> <50> <49> <51> Remark WR0 and WR1 are high level. R01UH0015EJ0300 Rev.3.
PAGE 801
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (b) Write cycle (CLKOUT asynchronous): In separate bus mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to WRm↓) tSAWR <52> (1 + tASW + tAHW)T − 27 ns Address hold time (from WRm↑) tHAWR <53> 0.5T − 6 ns WRm low-level width tWWRL <54> (0.
PAGE 802
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Separate Bus Mode TW T1 T2 CLKOUT (output) A0 to A21 (output) <53> <58> AD0 to AD15 (I/O) Hi-Z Hi-Z <55> <57> <52> <56> <54> WR0, WR1 (output) <62> <60> <59> <61> WAIT (input) <63> <65> <64> <66> Remark RD is high level. R01UH0015EJ0300 Rev.3.
PAGE 803
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous): In separate bus mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 804
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous): In separate bus mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 805
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (3) Bus hold (a) CLKOUT asynchronous (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit HLDRQ high-level width tWHQH <78> T + 10 ns HLDAK low-level width tWHAL <79> T − 15 ns Delay time from HLDAK↑ to bus output tDHAC <80> −3 ns Delay time from HLDRQ↓ to HLDAK↓ tDHQHA1 <81> Delay time from HLDRQ↑ to HLDAK↑ tDHQHA2 <82> 0.5T (2n + 7.5)T + 26 ns 1.
PAGE 806
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol HLDRQ setup time (to CLKOUT↓) Conditions MIN. MAX.
PAGE 807
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Power On/Power Off/Reset Timing (TA = −40 to +85°C, VSS = AVSS = EVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. EVDD↑ → VDD↑ tREL <87> 0 EVDD↑ → AVREF0, AVREF1↑ tREA <88> 0 VDD↑ → RESET↑ tRER <89> 500 + tREG RESET low-level width tWRSL <90> Analog noise elimination (during flash erase/ MAX.
PAGE 808
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Key Return Timing (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit KRn high-level width tWKRH Analog noise elimination 500 ns KRn low-level width tWKRL Analog noise elimination 500 ns Remark n = 0 to 7 Timer Timing (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX.
PAGE 809
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSIB Timing (1) Master mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKBn cycle time SCKBn high-/low-level width Symbol Conditions MIN. MAX. Unit tKCY1 <94> 125 ns tKH1, <95> tKCY1/2 − 8 ns <96> 27 ns 27 tKL1 SIBn setup time (to SCKBn↑) tSIK1 SIBn hold time (from SCKBn↑) tKSI1 <97> Delay time from SCKBn↓ to SOBn output tKSO1 <98> Remark ns 27 ns MAX.
PAGE 810
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS I C Bus Mode (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) 2 Parameter Symbol Normal Mode High-Speed Mode MIN. MAX. MIN. MAX. Unit SCL0n clock frequency fCLK 0 100 0 400 kHz Bus free time tBUF <99> 4.7 − 1.3 − μs tHD: STA <100> 4.0 − 0.6 − μs SCL0n clock low-level width tLOW <101> 4.7 − 1.3 − μs SCL0n clock high-level width tHIGH <102> 4.0 − 0.
PAGE 811
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 I C Bus Mode <101> <102> SCL0n (I/O) <107> <106> <104> <105> <103> <100> <109> <108> <100> SDA0n (I/O) <99> Stop condition Remark <106> Start condition <107> Restart condition Stop condition n = 0 to 2 A/D Converter (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, 3.0 V ≤ AVREF0 ≤ 3.6 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 bit ±0.6 %FSR 24 μs Zero scale error ±0.
PAGE 812
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS D/A Converter (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, 3.0 V ≤ AVREF1 ≤ 3.6 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. Resolution MAX. Unit 8 bit Overall error R = 2 MΩ ±1.2 %FSR Settling time C = 20 pF 3 μs Note 1 Output resistor RO Reference voltage AVREF1 AVREF1 current Note 2 Output data 55H 6.42 3.0 AIREF1 D/A conversion operating 1 D/A conversion stopped kΩ 3.6 V 2.
PAGE 813
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS RAM Retention Detection (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VRAMH Supply voltage rise time tRAMHTH VDD = 0 to 2.85 V Response time tRAMHD After VDD reaches 2.1 V Minimum pulse width tRAMHW Note Note MIN. TYP. MAX. Unit 1.9 2.0 2.1 V 0.002 ms 0.2 3.0 ms 0.2 ms Time required to detect the detection voltage and set the RAMS.RAMF bit.
PAGE 814
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics (TA = −40 to +85°C, VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = AVSS = 0 V, CL = 50 pF) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Operating frequency fCPU 2.5 32 MHz Supply voltage VDD 2.85 3.
PAGE 815
V850ES/JG3 CHAPTER 29 ELECTRICAL SPECIFICATIONS (3) Programming characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Chip erase time fXX = 32 MHz, batch erase 105 ms Write time per 256 bytes fXX = 32 MHz 2.0 ms Block internal verify time fXX = 32 MHz 10 ms Block blank check time fXX = 32 MHz 0.5 ms Flash memory fXX = 32 MHz 30 ms information setting time Remark Block size = 4 Kbytes R01UH0015EJ0300 Rev.3.
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V850ES/JG3 CHAPTER 30 PACKAGE DRAWING CHAPTER 30 PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) HD detail of lead end D L1 108 109 73 72 A3 c L E HE Lp (UNIT:mm) 144 1 37 36 ZE b x M S e ZD A A2 S y S NOTE Each lead centerline is located within 0.08mm of its true position at maximum material condition. ITEM D DIMENSIONS 20.00±0.20 E 20.00±0.20 HD 22.00±0.20 HE 22.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 0.25 b 0.20 c 0.125 L 0.50 Lp 0.60±0.
PAGE 817
V850ES/JG3 CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS The V850ES/JG3 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http:// www2.renesas.com/pkg/en/mount/index.html) Table 31-1.
PAGE 818
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/JG3. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
PAGE 819
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS Figure A-1.
PAGE 820
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included Software package for V850 this package. microcontrollers Part number: μS××××SP850 Remark ×××× in the part number differs depending on the host machine and OS used. μS××××SP850 ×××× Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Supply Medium CD-ROM A.
PAGE 821
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using IECUBE QB-V850ESSX2 The system configuration when connecting the QB-V850ESSX2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible. Figure A-2.
PAGE 822
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS Figure A-2. System Configuration (When Using QB-V850ESSX2) (2/2) Notes 1. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/ja/ods/index.html 2. Under development 3. Supplied with the device depending on the ordering number. • When QB-V850ESSX2-ZZZ is ordered The exchange adapter and the target connector are not supplied. • When QB-V850ESSX2-S100GC is ordered The QB-100GC-EA-01S and QB-100GC-TC-01S are supplied.
PAGE 823
V850ES/JG3 A.4.2 APPENDIX A DEVELOPMENT TOOLS When using MINICUBE QB-V850MINI (1) On-chip emulation using MINICUBE The system configuration when connecting MINICUBE to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-3.
PAGE 824
V850ES/JG3 A.4.3 APPENDIX A DEVELOPMENT TOOLS When using MINICUBE2 QB-MINI2 The system configuration when connecting MINICUBE2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-4. System Configuration of On-Chip Emulation System <4> <3> <1> <5> V850ES/JG3 M IN IC U BE 2 <6> <2> Software Target system <1> Host machine PC with USB ports <2> Software The integrated debugger ID850QB, device file, etc. Download the device file from the Renesas Electronics website.
PAGE 825
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) SM850 (under development) This simulator is used with V850 microcontrollers. SM850 is Windows-based software. System simulator Debugging of C source and assembler files is possible during simulation of the target system operation on the host machine. By using SM850, logic verification and performance verification of applications can be performed independently from hardware development.
PAGE 826
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to μITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than the RX850. Part number: μS××××RX703000-ΔΔΔΔ (RX850) μS××××RX703100-ΔΔΔΔ (RX850 Pro) RX-FS850 This is a FAT file system function. (File system) It is a file system that supports the CD-ROM file system function.
PAGE 827
V850ES/JG3 APPENDIX A DEVELOPMENT TOOLS A.7 Flash Memory Writing Tools Flashpro IV Flash programmer dedicated to microcontrollers with on-chip flash memory. (part number: PG-FP4) Flash programmer QB-MINI2 (MINICUBE2) On-chip debug emulator with programming function. FA-100GC-8EU-A Flash memory writing adapter used connected to the Flashpro IV, etc. (not wired). Flash memory writing adapter FA-70F3353GC-8EA-RX Flash memory writing adapter used connected to the Flashpro IV, etc. (already wired).
PAGE 828
V850ES/JG3 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2 Differences between the V850ES/JG3 and V850ES/JG2 are shown below. For details, refer to each corresponding section. Table B-1. Major Differences Between V850ES/JG3 and V850ES/JG2 (1/2) Major Differences V850ES/JG3 V850ES/JG2 Refer to: BVDD, BVSS pins Changed to EVDD, EVSS pins Provided Throughout Introduction: Minimum instruction 31.25 ns 50 ns 1.
PAGE 829
V850ES/JG3 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2 Table B-1. Major Differences Between V850ES/JG3 and V850ES/JG2 (2/2) Major Differences Electrical Operating condition V850ES/JG3 V850ES/JG2 fXX = 2.5 to 32 MHz fXX = 2.5 to 20 MHz Internal oscillator 220 kHz (TYP.) 200 kHz (TYP.) characteristics (min. and max.
PAGE 830
V850ES/JG3 APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX (1/10) Symbol ADA0CR0 Name Unit Page A/D conversion result register 0 ADC 417 ADA0CR0H A/D conversion result register 0H ADC 417 ADA0CR1 A/D conversion result register 1 ADC 417 ADA0CR1H A/D conversion result register 1H ADC 417 ADA0CR2 A/D conversion result register 2 ADC 417 ADA0CR2H A/D conversion result register 2H ADC 417 ADA0CR3 A/D conversion result register 3 ADC 417 ADA0CR3H A/D conversion result regis
PAGE 831
V850ES/JG3 APPENDIX C REGISTER INDEX (2/10) Symbol Name Unit Page CB0RX CSIB0 receive data register CSI 487 CB0RXL CSIB0 receive data register L CSI 487 CB0STR CSIB0 status register CSI 494 CB0TIC Interrupt control register INTC 651 CB0TX CSIB0 transmit data register CSI 487 CB0TXL CSIB0 transmit data register L CSI 487 CB1CTL0 CSIB1 control register 0 CSI 488 CB1CTL1 CSIB1 control register 1 CSI 491 CB1CTL2 CSIB1 control register 2 CSI 492 CB1RIC Interrupt control
PAGE 832
V850ES/JG3 APPENDIX C REGISTER INDEX (3/10) Symbol Name Unit Page CB4TX CSIB4 transmit data register CSI 487 CB4TXL CSIB4 transmit data register L CSI 487 CCLS CPU operation clock status register CG 182 CKC Clock control register CG 185 CLM Clock monitor mode register CLM 703 CRCD CRC data register CRC 720 CRCIN CRC input register CRC 720 CTBP CALLT base pointer CPU 33 CTPC CALLT execution status saving register CPU 32 CTPSW CALLT execution status saving register
PAGE 833
V850ES/JG3 APPENDIX C REGISTER INDEX (4/10) Symbol Name Unit Page DSA2L DMA source address register 2L DMA 614 DSA3H DMA source address register 3H DMA 614 DSA3L DMA source address register 3L DMA 614 DTFR0 DMA trigger factor register 0 DMA 619 DTFR1 DMA trigger factor register 1 DMA 619 DTFR2 DMA trigger factor register 2 DMA 619 DTFR3 DMA trigger factor register 3 DMA 619 DWC0 Data wait control register 0 BCU 161 ECR Interrupt source register CPU 30 EIPC Interrup
PAGE 834
V850ES/JG3 APPENDIX C REGISTER INDEX (5/10) Symbol Name Unit Page IMR3 Interrupt mask register 3 INTC 653 IMR3H Interrupt mask register 3H INTC 653 IMR3L Interrupt mask register 3L INTC 653 INTF0 External falling edge specification register 0 INTC 665 INTF3 External falling edge specification register 3 INTC 666 INTF9H External falling edge specification register 9H INTC 667 INTR0 External rising edge specification register 0 INTC 665 INTR3 External rising edge specificati
PAGE 835
V850ES/JG3 APPENDIX C REGISTER INDEX (6/10) Symbol Name Unit Page PF3H Port 3 function register H Port 79 PF3L Port 3 function register L Port 79 PF4 Port 4 function register Port 82 PF5 Port 5 function register Port 86 PF9 Port 9 function register Port 96 PF9H Port 9 function register H Port 96 PF9L Port 9 function register L Port 96 PFC0 Port 0 function control register Port 72 PFC3 Port 3 function control register Port 77 PFC3H Port 3 function control register H
PAGE 836
V850ES/JG3 APPENDIX C REGISTER INDEX (7/10) Symbol Name Unit Page PMC3 Port 3 mode control register Port 76 PMC3H Port 3 mode control register H Port 76 PMC3L Port 3 mode control register L Port 76 PMC4 Port 4 mode control register Port 81 PMC5 Port 5 mode control register Port 84 PMC9 Port 9 mode control register Port 91 PMC9H Port 9 mode control register H Port 91 PMC9L Port 9 mode control register L Port 91 PMCCM Port CM mode control register Port 98 PMCCT Port
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V850ES/JG3 APPENDIX C REGISTER INDEX (8/10) Symbol Name Unit Page SYS System status register CPU 60 TM0CMP0 TMM0 compare register 0 Timer 377 TM0CTL0 TMM0 control register 0 Timer 378 TM0EQIC0 Interrupt control register INTC 651 TP0CCIC0 Interrupt control register INTC 651 TP0CCIC1 Interrupt control register INTC 651 TP0CCR0 TMP0 capture/compare register 0 Timer 198 TP0CCR1 TMP0 capture/compare register 1 Timer 200 TP0CNT TMP0 counter read buffer register Timer 202
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V850ES/JG3 APPENDIX C REGISTER INDEX (9/10) Symbol Name Unit Page TP3CNT TMP3 counter read buffer register Timer 202 TP3CTL0 TMP3 control register 0 Timer 192 TP3CTL1 TMP3 control register 1 Timer 192 TP3IOC0 TMP3 I/O control register 0 Timer 194 TP3IOC1 TMP3 I/O control register 1 Timer 195 TP3IOC2 TMP3 I/O control register 2 Timer 196 TP3OPT0 TMP3 option register 0 Timer 197 TP3OVIC Interrupt control register INTC 651 TP4CCIC0 Interrupt control register INTC 651 T
PAGE 839
V850ES/JG3 APPENDIX C REGISTER INDEX (10/10) Symbol Name Unit Page TQ0IOC1 TMQ0 I/O control register 1 Timer 284 TQ0IOC2 TMQ0 I/O control register 2 Timer 285 TQ0OPT0 TMQ0 option register 0 Timer 286 TQ0OVIC Interrupt control register INTC 651 UA0CTL0 UARTA0 control register 0 UART 453 UA0CTL1 UARTA0 control register 1 UART 476 UA0CTL2 UARTA0 control register 2 UART 478 UA0OPT0 UARTA0 option control register 0 UART 455 UA0RIC Interrupt control register INTC 651 UA0R
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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST APPENDIX D INSTRUCTION SET LIST D.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results.
PAGE 841
V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a. store-memory (a, b, c) Write data b into address a in size c. load-memory-bit (a, b) Read bit b of address a.
PAGE 842
V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change 0 Clear to 0 X Set or cleared in accordance with the results. R Previously saved values are restored.
PAGE 843
V850ES/JG3 APPENDIX D INSTRUCTION SET LIST D.
PAGE 844
V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) i r l 3 3 3 1 1 1 CY OV S Z SAT DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H DI 0000011111100000 PSW.
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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) i r l 1 1 Note CY OV S Z SAT 11 Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] 0000000000100000 Other than regID = PSW 1 1 1 regID = PSW 1 1 1 1 1 Note × × × × 0 × × × Note 12 LD.
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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock i r l CY OV S Z SAT OR reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] 1 1 1 0 × × ORI imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) 1 1 1 0 × × i i i i i i i i i i i i i i i i PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp–4,GR[reg in list12],Word) LLLLLLLLLLL00001 sp←sp–4 n+1 n+1 n+1 Note 4 Note 4 Note 4 repeat
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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) i r l 3 3 3 CY OV S Z SAT × Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] 0000000011100000 Z flag←Not(Load-memory-bit(adr,reg2)) 3 3 × 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,reg2,1) SHL
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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock i r l CY OV S Z SAT SUB reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] 1 1 1 × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] 1 1 1 × × × × SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1) 5 5 5 1 1 1 1 1 1 3 3 3 1 1 1 0 × × 3 3 3 PC←(PC+2) + (sign-extend (Load-memory (adr,Half
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V850ES/JG3 APPENDIX D INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Higher 4 bits of imm9. 14.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS APPENDIX E LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 3 Soft Classification (2/36) Function CPU functions Details of Function Setting data to special registers Cautions Page Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1). p. 58 When a store instruction is executed to store data in the command register, p. 58 interrupts are not acknowledged.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Classification Details of Function Port functions PM1 register When using one of the P10 and P11 pins as an I/O port and the other as a D/A p. 73 output pin, do so in an application where the port I/O level does not change during D/A output.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Soft Chapter 4 Hard Classification (4/36) Function Port functions Details of Function Cautions Page Port 9 The P90 to P97, P99, P910, and P912 to P915 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. p. 89 P9 register To read/write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the P9H register. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 4 Soft Classification (5/36) Function Port functions Details of Function Cautions on switching from port mode to alternatefunction mode Cautions Page To switch from the port mode to alternate-function mode in the following order.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 5 Soft Classification (6/36) Function Bus control functions Details of Function Cautions Page Pin status when When a write access is performed to the internal ROM area, address, data, and internal ROM control signals are activated in the same way as access to the external memory area. p. 150 EXIMC register Set the EXIMC register from the internal ROM or internal RAM area before making an external access.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 6 Soft Classification (7/36) Function Details of Function Clock RCM register generation function PLLCTL register Cautions Page p. 182 The internal oscillator cannot be stopped while the CPU is operating on the internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1. p. 182 The internal oscillator oscillates if the CCLS.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 7 Soft Classification (8/36) Function 16-bit timer/ event counter P (TMP) Details of Function Cautions Page TPnIOC2 register The TPnETS1 and TPnETS0 bits are valid only when the external trigger pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 010) or the oneshot pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 = 011) is set. p. 196 TPnOPT0 register Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Chapter 7 Chapter 8 Soft Classification (9/36) Function 16-bit timer/ event counter P (TMP) Details of Function Cautions Page TPnIOC0, TPnOE0, TPnOL0 bits Clear this bit to 0 when the TOPn0 pin is not used in the external trigger pulse output mode. p. 224 Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 p. 228 register last.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 8 Soft Classification (10/36) Function Details of Function 16-bit TQ0IOC1 timer/ register event counter Q (TMQ) TQ0IOC2 register TQ0OPT0 register Cautions Page Rewrite the TQ0IS7 to TQ0IS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 8 Soft Classification (11/36) Function 16-bit timer/ event counter Q (TMQ) Details of Function Cautions Page When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TQ0CTL1.TQ0EEE bit to 0). p. 296 TQ0CTL1.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Chapter 9 Chapter 10 Soft Classification (12/36) Function 16-bit interval timer M (TMM) Watch timer functions Details of Function TM0CTL0 register Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0. When changing the value of TM0CE from 0 to 1, it is not possible to set the value of the TM0CKS2 to TM0CKS0 bits simultaneously. p. 378 Be sure to clear bits 3 to 6 to “0”. p. 378 pp. Do not set the TM0CMP0 register to FFFFH.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 11 Soft Classification (13/36) Function Details of Function Cautions Page Watchdog WDTM2 register If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly timer 2 generated and the counter is reset. function To intentionally generate an overflow signal, write data to the WDTM2 register only twice, or write a value other than “ACH” to the WDTE register only once.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Soft Chapter 13 Hard Classification (14/36) Function A/D converter Details of Function Cautions Page p. 409 ANI0 to ANI11 pins Make sure that the voltages input to the ANI0 to ANI11 pins do not exceed the rated values. In particular if a voltage of AVREF0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 13 Soft Classification (15/36) Function Details of Function Cautions Page A/D converter Conversion time selection in high-speed conversion mode (ADA0HS1 bit = 1) Set as 2.6 μs ≤ conversion time ≤ 10.4 μs. p. 414 In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input are prohibited during the stabilization time. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 13 Soft Classification (16/36) Function Details of Function A/D External trigger converter mode Cautions Page To select the external trigger mode, set the high-speed conversion mode. Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). p. 423 Timer trigger mode To select the timer trigger mode, set the high-speed conversion mode.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Hard Chapter 13 Soft Classification (17/36) Function Details of Function A/D Reading converter ADA0CRn register Cautions Page When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is p. 436 written, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before writing to the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Function D/A converter Soft Chapter 14 Hard Classification (18/36) Details of Function D/A converter Cautions Page DAC0 and DAC1 share the AVREF1 pin. p. 442 DAC0 and DAC1 share the AVSS pin. The AVSS pin is also shared by the A/D converter. p. 442 DA0M register The output trigger in the real-time output mode (DA0MDn bit = 1) is as follows.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 15 Soft Classification (19/36) Function Details of Function Asynchro- UART nous serial reception interface A (UARTA) Reception errors Cautions Page The operation during reception is performed assuming that there is only one stop bit. A second stop bit is ignored. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Chapter 15 Chapter 16 Soft Classification (20/36) Function Details of Function Asynchro- Start up nous serial UARTAn interface A (UARTA) 3-wire variablelength serial I/O (CSIB) Cautions Page Start up the UARTAn in the following sequence. <1> Set the UAnCTL0.UAnPWR bit to 1. <2> Set the ports. <3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1. p. 483 Stop UARTAn Stop the UARTAn in the following sequence. <1> Set the UAnCTL0.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 16 Soft Classification (21/36) Function 3-wire variablelength serial I/O (CSIB) Details of Function Cautions Page Baud rage generation Set fBRGm to 8 MHz or lower. p. 531 When transferring transmit data and receive data using DMA transfer When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 17 Soft Classification (22/36) Function Details of Function 2 I C bus IICC0 to IICC2 registers IICS0 to IICS2 registers Cautions Page Set the SPTn bit to 1 only in master mode. However, when the IICRSVn bit is 0, the SPTn bit must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. For details, see 17.15 Cautions. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Chapter 17 Chapter 18 Soft Classification (23/36) Function 2 I C bus Details of Function Cautions Page When communication among other devices are in progress When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications p. 596 among other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 18 Soft Classification (24/36) Function Details of Function DMA DSA0 to DSA3 function registers (DMA controller) DDA0 to DDA3 registers DBC0 to DBC3 registers DADC0 to DADC3 registers Cautions Page When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are read. If reading and updating conflict, the value being updated may be read (see 18.13 Cautions). p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 18 Soft Classification (25/36) Function Details of Function DMA DCHC0 to function DCHC3 (DMA registers controller) DTFR0 to DTFR3 registers Cautions Page The TCn bit is read-only. p. 618 The INITn and STGn bits are write-only. p. 618 Be sure to clear bits 6 to 3 of the DCHCn register to 0. p. 618 When DMA transfer is completed (when a terminal count is generated), the Enn bit is cleared to 0 and then the TCn bit is set to 1.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 18 Soft Classification (26/36) Function Details of Function DMA function (DMA controller) Caution for DMA transfer executed on internal RAM Cautions Page When executing the following instructions located in the internal RAM, do not execute a DMA transfer that transfers data to/from the internal RAM (transfer source/destination), because the CPU may not operate correctly afterward.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 18 Soft Classification (27/36) Function DMA function (DMA controller) Details of Function Cautions Page DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) <4> Again, clear the Enn bit of the channel to be forcibly terminated. p. 632 If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the internal RAM, execute this operation once more.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 18 Soft Classification (28/36) Function Details of Function DMA DMA start factor function (DMA controller) Soft Page Do not start two or more DMA channels with the same start factor. If two or more channels are started with the same factor, DMA for which a channel has already been set may be started or a DMA channel with a lower priority may be acknowledged earlier than a DMA channel with a higher priority. The operation cannot be guaranteed.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 19 Soft Classification (29/36) Function Details of Function Interrupt/ ISPR register exception processing function Cautions Page If an interrupt is acknowledged while the ISPR register is being read in the p. 655 interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set by acknowledging the interrupt may be read.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Chapter 20 Chapter 21 Soft Classification (30/36) Function Key interrupt function Standby function Details of Function KRM register Cautions Page Rewrite the KRM register after once clearing the KRM register to 00H. p. 672 If the KRM register is changed, an interrupt request signal (INTKR) may be p. 672 generated. To prevent this, change the KRM register after disabling interrupts (DI) or masking, then clear the interrupt request flag (KRIC.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Chapter 21 Soft Classification (31/36) Function Standby function Details of Function Cautions Page Releasing IDLE2 mode The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released. p. 682 STOP mode Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Soft Chapter Chapter 23 Chapter 22 Hard, Soft Classification (32/36) Function Details of Function Soft Page Reset function Hardware status The OCDM register is initialized by the RESET pin input. Therefore, note with on RESET pin caution that, if a high level is input to the P05/DRST pin after a reset release input before the OCDM.OCDM0 bit is cleared, the on-chip debug mode is entered. For details, see CHAPTER 4 PORT FUNCTIONS. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Hard, soft Chapter Chapter 27 Chapter 28 Hard Classification (33/36) Function Flash memory On-chip debug function Details of Function Cautions Page FA-144GJ-UEN-A Wire the FLMD1 pin as shown below, or connect it to GND on board via a pulldown resistor. p. 733 Supply a clock by creating an oscillator on the flash writing adapter (enclosed by the broken lines). p. 733 Do not input a high level to the DRST pin. p.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Hard Chapter Chapter 28 Chapter 29 Soft Classification (34/36) Function On-chip debug function Electrical specifications Details of Function Cautions (other than DUC) Cautions Page The standby mode is released by the pseudo RRM function and DMM function if one of the following conditions is satisfied.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Soft Chapter 29 Hard Classification (35/36) Function Electrical specifications Details of Function Subclock oscillator characteristics Cautions Page When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines.
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V850ES/JG3 APPENDIX E LIST OF CAUTIONS Chapter Details of Function Cautions Page When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and “write only”. Example (P: Write, E: Erase) Shipped product ⎯⎯→P→E→P→E→P: 3 rewrites Shipped product →E→P→E→P→E→P: 3 rewrites p. 799 RX850, RX850 Pro To purchase the RX850 or RX850 Pro, first fill in the purchase application form and sign the license agreement. p.
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V850ES/JG3 APPENDIX F REVISION HISTORY APPENDIX F REVISION HISTORY F.1 Major Revisions in This Edition Page Description p. 474 Modification of Caution in 15.6.10 Receive data noise filter p. 474 Modification of Figure 15-15. Timing of RXDAn Signal Judged as Noise p. 798 Modification of Flash Memory Programming Characteristics p. 799 Addition of Remark to CHAPTER 29 (3) Programming characteristics F.
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V850ES/JG3 User’s Manual: Hardware Publication Date: Rev.3.
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http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
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V850ES/JG3 R01UH0015EJ0300