Technical information

Section 3 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531, and SH72531FCC
Rev. 2.00 Feb. 18, 2009 Page 66 of 94
REJ10J1938-0200
Table 3.15 Items Displayed in the [EVA AUD Trace] Window (cont.)
Column Contents
Bus Displays the type of cycles accessed.
M-BUS: M-bus
I-BUS: I-bus
R/W Displays whether data access is read from or written to.
READ: Read access
WRITE: Write access
Size Displays the access size.
BYTE: Byte size
WORD: Word size
LONG: Longword size
Data Displays the data value.
Instruction Displays mnemonics of the execution instructions.
Time stamp Displays the timestamp. The internal clock value is used.
When the value is D’2199023255550, an overflow occurs and the value
becomes D’0 (about three hours when Iφ is 200 MHz).
Source Displays the C/C++ or assembly source of an address that has been acquired
by trace.
Label Displays label information.
(6) Notes on EVA AUD Trace
1. In the acquisition of trace information on both M-bus (CPU) and I-bus (DMAC or A-DMAC)
access to the same areas of the internal RAM (ERAM) and internal ROM, the actual orders of
memory access and of the output of trace information will be different. While data-trace
information is acquired at the time of completion of bus access, the actual timing of memory
access differs from the timing of the end of the bus cycle. Access to internal RAM via the M-
bus is in synchronization with the internal clock (φ) and so is faster than access to internal
RAM via the I-bus. Accordingly, the order of memory access and order of the acquisition of
trace information will differ in some cases. For example, in access to the internal RAM etc. via
the I-bus, the access to internal RAM will be completed before the I-bus access; if the next
access is via the M-bus, information on the later M-bus access will be the first to be output as
trace information.
2. Instruction-execution information is not acquired between branches where the timestamp
overflows.