User`s manual

SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7766
R20UT2190EJ0100 Rev.1.00 Page 32 of 34
Aug 09, 2012
Table 2.10 shows the measurement items and methods that are mainly used.
Table 2.10 Main Measurement Items
Main Measurement Item Measurement Method
Elapsed time Number of elapsed cycles x CPU clock cycles
Number of execution instructions Number of valid instructions issued + number of cases of
simultaneous execution of two instructions
Number of interrupts accepted Number of exceptions accepted
Number of instruction fetches (for
both cache and non-cache)
Number of memory accesses in an opcode
Instruction-cache hit ratio (Number of instruction-cache accesses– instruction-cache
miss counts)/instruction-cache access counts
Number of operand accesses (for
both cache and non-cache)
Number of memory accesses in an operand (read) + number
of memory accesses in an operand (write)
Operand-cache hit ratio (read) (Number of operand-cache accesses (read) – number of
operand-cache misses (read))/number of operand-cache
accesses (read)
Operand-cache hit ratio (write) (Number of operand-cache accesses (write) – number of
operand-cache misses (write))/ number of operand-cache
accesses (write)
Operand-cache hit ratio (Number of operand-cache accesses (read) + number of
operand-cache accesses (write) – number of operand-cache
misses (read) – number of operand-cache misses
(write))/(number of operand-cache accesses (read) + number
of operand-cache accesses (write))
System bus: occupied rate of
request bus
(The equivalent CPU clock value of the number of
requests)/number of elapsed cycles
System bus: occupied rate of
response bus
(The equivalent CPU clock value of the number of
responses)/number of elapsed cycles
Each measurement condition is also counted when conditions in table 2.11 are generated.
Table 2.11 Performance Measurement Conditions to be Counted
Measurement Condition Notes
No caching due to the
settings of TLB cacheable
bit
Counted for accessing the cacheable area.
Cache-on counting Accessing the non-cacheable area is counted less than the actual
number of cycles and counts. Accessing the cacheable, X/Y-RAM,
and U-RAM areas is counted more than the actual number of cycles
and counts.
Branch count The counter value is incremented by 2. This means that two cycles
are valid for one branch.
Notes: 1. In the non-realtime trace mode of the memory output trace, normal counting cannot be
performed because the generation state of the stall or the execution cycle is changed.
2. Since the clock source of the counter is the CPU clock, counting also stops when the
clock halts in the sleep mode.