User`s manual

SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7766
R20UT2190EJ0100 Rev.1.00 Page 29 of 34
Aug 09, 2012
Classification Type Measurement Item Option Note
TLB
performance
(cont)
TLB (cont) Number of ITLB
miss
IM The number of ITLB misses
for valid accesses (does not
include UTLB hits or misses).
Instruction bus
performance
Instruction Number of memory
accesses for
instruction fetch
MIF The number of memory
accesses by an instruction
fetch.
Accesses canceled by an
instruction-fetch bus are not
counted.
Instruction fetches, which
have been fetched in
anticipation of a branch but
not actually executed, are
counted.
Accesses by the PREFI
instruction are included.
Number of
instruction cache
access
IC The number of accesses for
an instruction cache during
memory access of the
opcode.
Number of
instruction cache
miss
ICM The number of cache misses
by an instruction cache
access (the number of
accesses to the outside of
the CPU core due to a cache
miss).
Number of internal-
RAM access for
instruction fetch
(XY-RAM or O-L
memory)
XL The number of accesses for
the XY or O-L memory in the
SH7766 during memory
accesses of the opcode.
Number of I-L
memory access for
instruction fetch
ILIF The number of accesses for
the I-L memory in the
SH7766 during memory
accesses of the opcode.
Number of U
memory access for
instruction fetch
ULF The number of accesses for
the U memory in the SH7766
during memory accesses of
the opcode.
Operand bus
performance
Access
count
Number of memory
access for operand
fetch (READ)
MR The number of memory
accesses by an operand read
(equal to loading on the
operand bus).
Accesses by the PREF
instruction or canceled
accesses are not included.
Number of memory
access for operand
fetch (WRITE)
MW The number of memory
accesses by an operand
write (equal to storing
memory on the operand bus).
Canceled accesses are not
included.