User`s manual

SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7766
R20UT2190EJ0100 Rev.1.00 Page 28 of 34
Aug 09, 2012
Table 2.9 Measurement Items
Classification Type Measurement Item Option Note
Disabled None Not measured.
CPU
performance
Cycle Elapsed cycles AC Except for power-on period;
counted by the CPU clock.
Cycles executed in
privileged mode
PM The number of privileged-
mode cycles among the
number of elapsed cycles.
Cycles for asserting
the SR.BL bit
BL The number of cycles when
the SR.BL bit = 1 among the
number of elapsed cycles.
Instruction Number of effective
instructions issued
I The number of execution
instructions = number of valid
instructions issued + number
of cases of simultaneous
execution of two instructions.
The number of valid
instructions means the
number of completed
instructions.
Number of 2
instruction executed
simultaneously
2I The number of times that two
instructions are executed
simultaneously among the
valid instructions issued.
Branch Number of
unconditional branch
BT The number of unconditional
branches other than
branches occurring after an
exception. However, RTE is
counted.
Exception,
interruption
Number of
exceptions accepted
EA Interrupts are included.
Number of interrupts
accepted
INT NMI is included.
Number of UBC
channel hit
UBC Performs OR to count the
number of channel-hits in the
CPU.
Stalled
cycle
Cycles stalled in full-
trace mode (with
multi-counts)
SFM All items are counted
independently.
Cycles stalled in full-
trace mode (without
multi-counts)
SF This item is not counted if the
stall cycle is generated
simultaneously with a stall
cycle that has occurred due
to instruction execution.
TLB
performance
TLB Number of UTLB
miss for instruction
fetch
UMI The number of TLB-miss
exceptions generated by an
instruction fetch (number of
EXPEVT sets).
Number of UTLB
miss for operand
fetch
UMO The number of TLB-miss
exceptions generated by an
operand access (number of
EXPEVT sets).