User`s manual
SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7766
R20UT2190EJ0100 Rev.1.00 Page 8 of 34
Aug 09, 2012
4. Reset Signals
The SH7766 reset signals are only valid during emulation started with clicking the GO or
STEP-type button. If these signals are enabled on the user system in command input wait
state, they are not sent to the SH7766.
Note: Do not break the user program when the PRESET# signal is being low and the WAIT
control signal is being active. A TIMEOUT error will occur. If the WAIT control signal
is fixed to active during break, a TIMEOUT error will occur at memory access.
5. Direct Memory Access Controller (DMAC)
The DMAC operates even when the emulator is used. When a data transfer request is
generated, the DMAC executes DMA transfer.
6. Memory Access during User Program Execution
When a memory is accessed from the memory window, etc. during user program execution,
the user program is resumed after it has stopped in the emulator to access the memory.
Therefore, realtime emulation cannot be performed.
The stopping time of the user program is as follows:
Environment:
SH7766: 534 MHz (CPU clock)
JTAG clock: 20 MHz (TCK clock)
When a one-byte memory is read from the command-line window, the stopping time will be
about 40 ms.
7. Memory Access during User Program Break
The emulator can download the program for the flash memory area (for details, refer to section
6.22, Download Function to the Flash Memory Area, in the SuperH
TM
Family E10A-USB
Emulator User’s Manual). Other memory write operations are enabled for the RAM area.
Therefore, an operation such as memory write or BREAKPOINT should be set only for the
RAM area.
8. Cache Operation during User Program Break
When the cache is enabled, the emulator accesses memory according to the following methods:
⎯ Writing to memory:
• Cache hit: Writes to the cache, then issues a single external write. The LRU is not
updated.
• Cache miss: Issues a single write. Neither writing to the cache nor updating of the LRU
proceeds.
⎯ Reading from memory:
• Cache hit: Reads from the cache. The LRU is not updated.
• Cache miss: Issues a single read. Neither filling of the cache nor updating of the LRU
proceeds.
Therefore, when memory read or write is performed during user program break, the cache state
does not change.
⎯ At breakpoint set: Disables the instruction cache.