User`s manual

SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7752
R20UT2163EJ0200 Rev. 2.00 Page 41 of 43
May 23, 2013
Classification Type Measurement Item Option Note
Operand Bus
performance
(cont)
Waited
cycle (cont)
Waited cycles for
operand cache miss
(READ)
WCMR The number of waited cycles
by an operand cache miss
(read) (however, the number
of waited cycles of cache fiII
is included due to contention).
Waited cycles for
operand cache miss
(WRITE)
WCMW The number of waited cycles
by an operand cache miss
(write).
Number of waited
cycles by an I-L
memory access for
operand fetch
(READ)
WILR The number of waited cycles
by an I-L memory access
(read) of an operand.
Number of waited
cycles by an I-L
memory access for
operand fetch
(WRITE)
WILW The number of waited cycles
by an I-L memory access
(write) of an operand.
System bus
performance
(only available
for Ch3 and
Ch4)
System bus Number of requests RQ The number of valid bus
cycles (cells) is counted by
the system bus clock.
Number of
responses
RS The number of valid bus
cycles (cells) is counted by
the system bus clock.
Waited cycles for
request
WRQ The cycles for an issued
request (req), that no
acceptance signal (gnt) is
issued to, are counted by the
system bus clock.
Even if the waits are issued
simultaneously for multiple
requests, they are counted as
1.
Waited cycles for
response
WRS The cycles for an issued
response (r_req), that no
acceptance signal (r_gnt) is
issued to, are counted by the
system bus clock.
Even if the waits are issued
simultaneously for multiple
requests, they are counted as
1.