User`s manual

SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7752
R20UT2163EJ0200 Rev. 2.00 Page 40 of 43
May 23, 2013
Classification Type Measurement Item Option Note
Operand bus
performance
(cont)
Access
count (cont)
Number of operand
cache access
(READ)
CR The number of operand-
cache reads during memory
access (read) of an operand.
Number of operand
cache access
(WRITE)
CW The number of operand-
cache reads during memory
access (write) of an operand.
Number of internal-
RAM access for
operand fetch
(READ) (XY-RAM or
O-L memory)
XLR The number of accesses to
XY or O-L memory in the
SH7752 during memory
access (read) of an operand.
(Accesses via the XY bus and
the operand bus are included.
When MOVX and MOVY are
executed simultaneously, it
increments one count
regardless of the read or
write.)
Number of internal-
RAM access for
operand fetch
(WRITE) (XY-RAM
or O-L memory)
XLW The number of accesses to
XY or O-L memory in the
SH7752 during memory
access (write) of an operand.
(Accesses via the XY bus and
the operand bus are included.
When MOVX and MOVY are
executed simultaneously, it
increments one count
regardless of the read or
write.)
Number of I-L
memory access for
operand fetch
(READ/WRITE)
ILRW The number of accesses to I-
L memory in the SH7752
during memory access
(read/write) of an operand.
Access
miss count
Number of operand
cache miss (READ)
CMR The number of cache misses
by an operand cache access
(read) (number of accesses to
the outside of the CPU core
due to a cache miss).
Cache misses are not
counted by the PREF
instruction.
Number of operand
cache miss (WRITE)
CMW The number of cache misses
by an operand cache access
(write) (number of accesses
to the outside of the CPU core
due to a cache miss).
Write-through accesses are
not counted. Cache misses
are not counted by the PREF
instruction.
Waited
cycle
Waited cycles for
operand fetch
(READ)
WOR The number of waited cycles
by a memory access (read) of
an operand.
Waited cycles for
operand fetch
(WRITE)
WOW The number of waited cycles
by a memory access (write) of
an operand.