User`s manual

SuperH Family E10A-USB Emulator for Multi-core Microcomputers Section 2 Emulator Functions
R20UT0363EJ0500 Rev. 5.00 Page 18 of 296
Aug 10, 2012
Notes: 1. Memory access during user program execution:
When memory is accessed from the memory window, etc. during execution of the user
program, execution stops for the memory access and is then resumed. Therefore, realtime
emulation cannot be performed.
The stopping time of the user program is as follows:
Environment:
Host computer: CORE
TM
2 CPU T7600 2.33 GHz
SH7265: CPU clock 66.6 MHz
JTAG clock: 2.5 MHz
When a one-byte memory is read from the command-line window, the stopping time
will be about 70 ms.
2. Memory access during user program break:
The program can also be downloaded for the flash memory area by the emulator.
Other memory write operations are enabled for the RAM area and the internal flash
memory. Therefore, an operation such as memory write or BREAKPOINT should be
set only for the RAM area and the internal flash memory. When the memory area can
be read by the MMU, do not perform memory write, BREAKPOINT setting, or
downloading.
3. Cache operation during user program break:
When cache is enabled in the device incorporating a cache, the emulator accesses the
memory by the following methods:
 At memory write: Writes through the cache, then writes to the memory or uses the
OCBWB instruction.
 At memory read: Does not change the cache write mode that has been set.
 At memory verify: Disables the cache for verification read.
Therefore, when memory read or write is performed during user program break, the
cache state will be changed.
In some devices to be debugged, the emulator accesses the memory by the following
methods:
 At memory write: Writes to the cache, then issues an external single write. The
LRU is not updated.
 At memory read: Reads memory from the cache. The LRU is not updated.