User`s manual
SuperH Family E10A-USB Emulator for Multi-core Microcomputers Section 5 Debugging
R20UT0363EJ0500 Rev. 5.00 Page 113 of 296
Aug 10, 2012
[Realtime trace]: Some trace information will not be output.
[Non realtime trace]: The CPU is made to wait for the output of trace data.
[Trace Mode 2]: Decides whether or not operation continues after the trace buffer of the emulator is full.
This can only be used when [AUD trace] or [User Memory trace] is selected.
[Trace continue]: Continue to acquire the latest information by overwriting the oldest trace
information.
[Trace stop]: Acquisition of trace information stops when the buffer is full.
[AUD Mode]: Depending on the target device for debugging, an 8-bit AUD pin mode may be selectable.
Refer to the additional document, Supplementary Information on Using the SHxxxx and
the online help for the specifications of devices. This mode is only valid when [AUD
trace] is selected.
[AUD trace Memory Size]: Set the size of the trace buffer memory for the emulator.
This mode is only valid when [AUD trace] is selected.
[AUD trace display range]: Set the range for display in the trace window.
This mode is only valid when [AUD trace] is selected.
[Start pointer] Traced data are displayed from the value set here.
[End pointer] Traced display are displayed up to the value set here.
[User Memory area]: Set the range for display in the trace window.
This mode is only valid when [User Memory trace] is selected.
[Start] Specify the first address of the region of memory where the results of tracing are to
be written.
[End address] Specify the last address of the region of memory where the results of tracing
are to be written.
[Trace Extend Mode]:
[Trace data is PPC] Output values of the performance counter to the trace window.
The specified contents are set by clicking on the [OK] button. If the [Cancel] button is clicked, the
dialog box is closed without the settings being made.
Also, settings other than those in the [Display Type] group box are common to the High-
performance Embedded Workshops for CPU0 and CPU1. Settings in the [Display Type] group box
are not common to the High-performance Embedded Workshops for CPU0 and CPU1.
Refer to the additional document Supplementary Information on Using the SHxxxx or the online
help for the specifications of devices.