User`s manual

SuperH Family E10A-USB Emulator for Multi-core Microcomputers Section 5 Debugging
R20UT0363EJ0500 Rev. 5.00 Page 109 of 296
Aug 10, 2012
[Master] Master device that generated the event:
CPU: CPU0 was the master
[Type] Type of the trace information:
BRANCH: Branch source
DESTINATION: Branch destination
MEMORY: Memory access
S_TRACE: Executed Trace(x) function
LOST: Lost trace information (only in the realtime mode)
CPU-WAIT: CPU was waiting for the output of the trace information
(only in the non-realtime mode)
[Branch Type] Type of the branch:
GENERAL: General branch
SUBROUTINE: Subroutine branch
EXCEPTION: Exception branch
[Bus] Display the access type of the cycle:
M-Bus: M bus
I-Bus: I bus
[R/W] Display whether access to data is reading or writing
READ: Read access
WRITE: Write access
[Address] Instruction address (AUD trace: If there is no base address in the trace buffer,
display the difference only)
[Data] Display the data value.
[Size] Display the size of access:
BYTE: Byte
WORD: Word
LONG: Longword
[Instruction] Instruction mnemonic
[Timestamp] No timestamp, value is fixed to 0
[Source] The C/C++ or assembly-language source program
[Label] Label information