User`s manual

SuperH Family E10A-USB Emulator for Multi-core Microcomputers Section 5 Debugging
R20UT0363EJ0500 Rev. 5.00 Page 107 of 296
Aug 10, 2012
[IP] The amount of acquired trace information
[CPU ID] Type of the CPU core:
CPU0: Trace is made for CPU0
CPU1: Trace is made for CPU1
[Master] Master device that generated the event.
CPU: CPU0 was the master.
DMA: The DMAC was the master.
[Type] Type of the trace information
BRANCH: Branch source
DESTINATION: Branch destination
MEMORY: Memory access
PC-RELATIVE: PC-relative access
INSTRUCTION: Instruction fetching from the external space
S_TRACE: Indicates execution of the Trace (x) function
OPERAND PRE-FETCH: Execution of the PREF instruction.
[Branch Type] Type of the branch:
GENERAL: General branch
SUBROUTINE: Subroutine branch
EXCEPTION: Exception branch
[Bus] Display the access type of the cycle:
F-Bus: F bus
M-Bus: M bus
I-Bus: I bus
DMA: Direct memory access
[R/W] Display whether access to data is reading or writing
READ: Read access
WRITE: Write access
[Address] Instruction address
[Data] Display the data value