user manual

Rev. 5.00, 09/03, page 305 of 760
T
1
T
W
T
W
T
B2
T
B1
T
W
T
B2
CKIO
A
25 to A4
A
3 to A0
CSn
RD/WR
RD
D31 to
D0
BS
WAIT
T
2
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
T
B1
Figure 10.29 Burst ROM Wait Access Timing