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Usage Notes Reference Book 16 M16C/62 (M16C/62A, M16C/62M) Group Usage Notes Reference Book Renesas 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
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Preface This book describes the M16C/62 (M16C/62A, M16C/62M) group's precautions for use, which contains paragraphs describing precautions of the user's manual and technical news relevant to these paragraphs. Please refer to this book when developing your systems. However, all of precautions are not contained in this book, please perform sufficient evaluation under systems development.
Mitsubishi microcomputers M16C / 62A Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 • When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Mitsubishi microcomputers M16C / 62A Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt) Note: Execute the setting above individually.
Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash Memory Version) Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.
Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (8) Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks.
Mitsubishi microcomputers Protect M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.1.3 Precaution for Protect (1) The write-enable bit of port 9 direction register and SI/Oi control register (i=3,4) goes to “0” when the next write instruction is executed after write-enabled state is readied.
Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.13 Precautions for Timer A (timer mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing shown in Figure 2.2.28 gets “FFFF16”.
Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.14 Precautions for Timer A (event counter mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing shown in Figure 2.2.
Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.15 Precautions for Timer A (one-shot timer mode) (1) At reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TAiOUT pin outputs “L” level.
Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.16 Precautions for Timer A (pulse width modulation mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode.
Mitsubishi microcomputers M16C / 62A Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.6 Precautions for Timer B (timer mode, event counter mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the flag to “1”. (2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing shown in Figure 2.3.12 gets “FFFF16”.
Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) (1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine.
Mitsubishi microcomputers M16C / 62A Group Clock-Synchronous Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O) Transmission/reception _______ ________ (1) With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmis________ sion side that the reception has become ready.
Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transmission (1) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1. Set the transmit enable bit (to “1”) 2. Write transmission data to the UARTi transmit buffer register ________ _______ 3.
Mitsubishi microcomputers M16C / 62A Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.10 Precautions for A-D Converter (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after an elapse of 1 µs or longer.
Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.15.4 Precautions in Power Control ______ (1) The processor does not switch to stop mode when the NMI pin is at “L” level. ____________ (2) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized.
Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.6 Precautions for External Bus (1) The external ROM version can operate only in the microprocessor mode, so be sure to perform the following: • Connect the CNVSS pin to Vcc.
Related to M16C/80, M16C/60, M16C/20 series devices. A GRADE MSC TECHNICAL NEWS No.M16C-09-9705 Note on using the A-D converter of the M16C/60 series MCU 1. Related devices M16C/60 series 2. Symptoms After A-D conversion is complete, if the CPU reads the A-D register at the same time as the A-D conversion result is being saved to A-D register, wrong A-D conversion value is saved into the A-D register. This happens when the internal CPU clock is selected from divided main clock or sub-clock.
Related to M16C/80, M16C/60, M16C/20 series devices. GRADE MESC TECHNICAL NEWS A No.M16C-11-9710 Note on dedicated input pin of the M16C/60 series MCU 1. Related devices M16C/60 series 2. Note on dedicated input pin When different power supplied to the system as shown in figure 1, and input voltage of unused dedicated input pin is larger than voltage of VCC pin, do not connect dedicated input pin and power supply directly. Connect to VCC via resistor (approximately 1kohm) as shown in figure 2.
Related to M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-12-9711 Note on the interrupt control register of the M16C/60 series MCU 1. Related devices M16C/60 series 2. Note Do not rewrite to interrupt control register when the interrupt enable flag is enable state ( I flag = "1" ). A rewrite instruction includes read modify write instructions such as BSET. 3.
Related to M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-13-9802 Supplemental Description of DMAC for the M16C/60, M16C/61 and M16C/62 Group MCUs 1. Related devices M16C/60, M16C/61 and M16C/62 groups 2. DMA enable bit The DMA enable bit is bit 3 of both DMA0 and DMA1 control registers. When the DMA enable bit is set to "1" the DMAC is in an active state and the following occurs: a.
No.M16C-13-9802 4.
Related to M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-14-9805 Precautions Regarding Writing to M16C/60, M16C/61, M16C/62 and M16C/63 Group MCUs Interrupt Control Registers 1. Related devices M16C/60, M16C/61, M16C/62 and M16C/63 groups With the M16C/60 series MCU, setting the interrupt priority level and clearing the interrupt request bit in the interrupt control registers should be done with interrupt disabled.
No.M16C-14-9805 4. Conditions to be checked for program already written Please confirm that at least one condition is met for both actions listed below. If any one of the conditions is met, the symptom will not occur. (1) When changing ILVL - I-FLAG is "0". (Interrupt disabled) (*Note) - The processor interrupt priority level (IPL) in the flag register is "7". - The ILVL changes from a lower level than IPL to a higher level. - The ILVL before and after the change is lower than IPL.
No.M16C-14-9805 5. Program examples The program examples are described as follow: (1) For assembler Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W FSET MEM, R0 I ; Dummy read. ; Enable interrupts.
Related to M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-17-9902 M16C/60 Group, M16C/61 Group, M16C/62 Group Precautions For Power Control State Transitions 1. Related devices M16C/60 group, M16C/61 group, M16C/62 group 2. Precautions Power control state transition is shown on the next page. Please change modes according to a directions of arrows. When count source of BCLK is changed from clock A to clock B (XIN to XCIN or XCIN to XIN), clock B needs to be stable before changing.
No.
Related to M16C/60 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-19-9903 MESC TECHNICAL NEWS 'No.M16C-16-9902' replace MESC TECHNICAL NEWS 'No.M16C-16-9902' has an error, so we will correct. Please replace old Technical News 'No.M16C-16-9902' to corrected Technical News 'M16C/60, M16C/61, M16C/62 Group Precautions for Setting Pull-up Resistors'. [Attached] Corrected Technical News 'No.M16C-19-9903' 'M16C/60, M16C/61, M16C/62 Group Precautions for Setting Pull-up Resistors' .....
GRADE A MESC TECHNICAL NEWS No.M16C-19-9903 M16C/60, M16C/61, M16C/62 Group Precautions for Setting Pull-up Resistors 1. Related devices M16C/60 group, M16C/61 group, M16C/62 group 2. Precautions Ports P0 to P10 can be set to apply a pull-up resistor by using the pull-up control registers. (1) M16C/60 Group, M16C/61 Group In Memory expansion mode or Microprocessor mode, the settings of pull-up control registers for ports P0 to P5 are invalid.
Related to M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-25-9905 M16C/60 , M16C/20 Series Precautions for Wait and Stop modes 1. Related devices M16C/60 Series , M16C/20 Series 2. Precautions The M16C has both WAIT and STOP modes. These modes can be used to reduce power consumption when the CPU is not required to perform any work.
No.M16C-25-9905 _______ 3.2 When using only hardware reset or NMI interrupt to cancel the STOP or WAIT modes, use the following algorithm to enter the STOP or WAIT modes. Set the interrupt enable flag (I flag) to “0” Change all interrupt priority levels to 0 WAIT instruction or all clock stop control bit set Insert 4 NOP instructions ; Disable interrupt ; Disable maskable interrupt ; Set the bit 0 of protect register to “1” before set the all clock stop control bit to “1” .
Related to M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-26-9905 M16C/61 , M16C/62 Group Precautions for UART2 1. Related devices M16C/61 Group, M16C/62 Group 2. Precautions When using UART2 in clock asynchronous serial I/O (UART) mode choose internal clock. If UART2 in clock asynchronous mode is used with external clock, then one of the following may occur; 2.
Related to M16C/60 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-32-9908 M16C/60 Series Precautions for Address Match Interrupt 1. Related devices M16C/60 Series 2. Precautions When using the address match interrupt, please observe the following usage conditions. (1) Address match interrupt for internal address. (2) Address match interrupt for external address and 16-bit bus. When external address and 8-bit bus, you can not use the address match interrupt for external address.
Related to M16C/80, M16C/60 series devices. Related to M16C/20 series devices (except for M30201 group devices). GRADE A MESC TECHNICAL NEWS No.M16C-39-9911 M16C Family Cautions for “Event counter mode” with Timer A 1. Affected devices • M16C/80 Group, M16C/60 Group, M16C/61 Group, M16C/62 Group (Included 3V version) • M16C/62A Group (Included 3V version), M16C/6N Group, M16C/6K Group, M16C/6V Group • M16C/6H Group, M16C/21 Group, M16C/24 Group 2.
Related to M16C/80, M16C/60 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-49-0004 M16C/80 Series, M16C/60 Series Cautions for Using Memory Expansion Mode or Microprocessor Mode 1. Affected devices • M16C/80 Series • M16C/60 Series 2. Cautions When the MCU enters wait mode while operating in memory expansion mode or microprocessor mode, a pin functioning as part of the address or data bus retains it's state on the bus before wait mode is entered.
Related to M16C/62 group devices. GRADE A MESC TECHNICAL NEWS No.M16C-54-0004 Difference between M16C/62 and M16C/62A (include low voltage version) 1. Affected devices • M16C/62 group {M16C/62, M16C/62L (low voltage version), M16C/62A, M16C/62M (low voltage version)} Table 1 shows the product list of M16C/62 and M16C/62A. Table 2 shows the product list of M16C/62L (low voltage version) and M16C/62M (low voltage version). Table 1.
No.M16C-54-0004 Table 2.
No.M16C-54-0004 Table 4. Differences between M16C/62L (low voltage version) and M16C/62M (low voltage version) M16C/62 group Mask ROM, Flash memory versions common Item Operation voltage/ frequency characteristics M16C/62L M16C/62M Vcc=2.7V to 3.6V ( f(XIN)=10MHz, No wait) Vcc=2.7V to 3.6V ( f(XIN)=10MHz, No wait) Vcc=2.4V to 3.6V ( f(XIN)=7MHz, No wait) Vcc=2.4V to 3.6V ( f(XIN)=7MHz, No wait) Vcc=2.2V to 3.
Related to M16C/80, M16C/60, M16C/20 series devices. GRADE A MESC TECHNICAL NEWS No.M16C-55-0006 M16C Family Cautions Using Data Registers that Include Write Only Bits 1. Affected devices • M16C Family 2. Cautions The registers shown in the table on the following page contain bits that will result in unknown data when read.
No.M16C-55-0006 Table 1.
No.M16C-55-0006 Table 4.
No.M16C-55-0006 Table 7.
No.M16C-55-0006 Table 10. Instruction table for Read Modify Write Function Mnemonic Bit manipulation BCLR, BNOT, BSET, BTSTC, BTSTS Shift ROLC, RORC, ROT, SHA, SHL Arithmetic ABS, ADC, ADCF, ADD, DEC, EXTS, INC, MUL, MULU, NEG, Logical AND, NOT, OR, XOR Jump ADJNZ, SBJNZ SBB, SUB 3. C language programming Figure 3 shows an example using C programming (1) #pragma ADDRESS char near UDF; void { UDF 0384h ‘Image of extract’ func(void) UDF = MOV.
GRADE MAEC TECHNICAL NEWS A No.M16C-69-0104 Supplemental Description for WAIT Peripheral Function Clock Stop Bit Classification Corrections and supplementary explanation of document Notes Knowhow ✔ Others Products Effected M16C/60 Series M16C/20 Series 1. Supplemental Description The WAIT peripheral function clock stop bit (CM02) is used to halt peripheral operations during WAIT mode.
Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Figure 1.10.4 shows the system clock control registers 0 and 1.
Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Wait Mode Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced.
Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated.
GRADE MAEC TECHNICAL NEWS A No.M16C-71-0105 Setting procedure of processor mode bits Classification Corrections and supplementary explanation of document ✔ Notes Knowhow Others Products Effected M16C/80 Series M16C/60 Series 1. Precautions Processor mode bits are allocated to bits 1 and 0 of the processor mode register 0. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode.
GRADE MAEC TECHNICAL NEWS A No.M16C-75-0110 Corrections and Supplementary Explanation for M16C/20 Series, M16C/60 Series, M16C/80 Series Data Sheet and User's Manual Classification ✔Corrections and supplementary explanation of document Notes Knowhow Others Products Effected M16C/20 Series (Except for M16C/24 Group) M16C/60 Series M16C/80 Series This is to inform you of the errors that have been found in the data sheets and user's manuals of the M16C/20, M16C/60 and M16C/80 Series.
No.M16C-75-0110 Location: Hardware, timer X (exist in M30201 Group), pulse period/pulse width measurement mode Error: The timer Xi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Xi mode register. Correction: Assume that the count start flag condition is "1" and then the Timer Xi overflow flag becomes "1". If the Timer Xi mode register has a write-access after next count cycle of the timer from the above condition, the Timer Xi overflow flag becomes "0".
MITSUBISHI SEMICONDUCTORS USAGE NOTES REFERENCE BOOK M16C/62 (M16C/62A, M16C/62M) Group Oct. First Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor Usage Notes Reference Book Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
M16C/62 (M16C/62A, M16C/62M) Group Usage Notes Reference Book 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
