Specifications
SH7670 Group Example of Cache Memory Setting
R01AN0300EJ0101 Rev. 1.01 Page 9 of 12
Oct. 15, 2010
3.2 Sample program list "main.c" (2)
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/* ==== Prototype declaration ==== */
void main(void);
/* ==== Macro definition ==== */
#define SDRAM_ADDR_CACHABLE (volatile unsigned char *)(0x0C100000)
#define SDRAM_ADDR_NON_CACHABLE (volatile unsigned char *)(0x2C100000)
/*""FUNC COMMENT""*************************************************************
* ID :
* Outline : Sample Program main
*-----------------------------------------------------------------------------
* Include : #include "iodefine.h"
*-----------------------------------------------------------------------------
* Declaration : void main(void)
*-----------------------------------------------------------------------------
* Function : Example of enabling / disabling cache memory.
* : After the SDRAM area has been initialized with the operand cache OFF,
* : a fill operation is performed with the operand cache ON,
* : and the cached area is compared with its shadow in the cache-disabled
space.
* : The operand cache is to be controlled.
*-----------------------------------------------------------------------------
* Argument : void
*-----------------------------------------------------------------------------
* ReturnValue : void
*-----------------------------------------------------------------------------
* Notice : In this sample program, the cache is flushed. Therefore,
* : a program for initialization that enables the cache will invalidate
* : the contents of the cache.
*""FUNC COMMENT END""*********************************************************/
void main(void)
{
int i;
unsigned char *ptr1, *ptr2;
/* ==== Disabling operand cache ==== */
io_set_cache( 0x00000108 ); /* Instruction cache enable *
* Operand cache flush *
* Write-back mode *
* Operand cache disable */
/* ---- Initializing SDRAM ---- */
ptr1 = SDRAM_ADDR_CACHABLE; /* Cache-enabled space */
for(i=0; i<16; i++){ /* Written to actual memory */
*ptr1++ = 0; /* as caching is disabled */
}
/* ==== Enabling operand cache ==== */
io_set_cache( 0x00000109 ); /* Instruction cache enable *
* Operand cache flush *
* Write-back mode *
* Operand cache enable */