Specifications

SH7670 Group Example of Cache Memory Setting

2.3 Description of the Sample Program

In the sample program, the instruction cache and operand cache are enabled, and then data equivalent to a single cache

line (16 bytes) are written to external memory (SDRAM) in write-back mode. In this case, the data are actually written

to the cache and not reflected in external memory (SDRAM) until the cache entry (line) is replaced. Contents of

external memory (SDRAM) are read out from a cache-disabled space after the fill operation, and compared with the

contents of the cache.

The section name for the cache manipulation function is adjusted so that the function is placed in a cache-disabled space.

2.4 Procedure for Processing by the Sample Program

Table 2 describes how the cache is set up by the sample program. Figure 3 shows a flow of processing by the sample

program.

Table 2 Cache Settings

Cache control register1

(CCR1)

H'FFFC 1000 H'0000 0109 ICE = "1": Enables the instruction cache

OCF = "1": Flushes the operand cache

WT = "0": Write-back mode

OCE = "1": Enables the operand cache

Main function

main

Enable the operand cache:

io_set_cache();

Fill the SDRAM area with 0

Fill the SDRAM area (cached area) with 0 × 55

Compare the values accessed in

a cache-enabled space with the values

accessed in a cache-disabled space

END

Disable the operand cache:

io_set_cache();

Figure 3 Flow of Processing of the Main Function

R01AN0300EJ0101 Rev. 1.01 Page 6 of 12

Oct. 15, 2010