Specifications

SH7670 Group Example of Cache Memory Setting
2.2 Procedure for Setting the Module Used
The procedure for setting up the caches is described below.
Cache control register 1 (CCR1) is used to set up the cache. Program code that manipulates the cache control registers
must be executed from an area for which caching is disabled. Also, access to areas for which caching has been enabled
must only proceed after the CCR1 register has been read.
This sample application also changes the interrupt mask to prevent the acceptance of interrupt processing that might
include access to the cache-enabled spaces while the cache mode is being updated.
Figure 2 is a flow chart showing an example of the procedure used to enable both the instruction cache and operand
cache.
START
END
Set the cache mode (CCR1)
ICF: Set the ICF (instruction cache flush) bit to 1
[Function] Flushes the instruction cache
(its contents are not written back to external memory).
ICE: Set the ICE (instruction cache enable) bit to 1
[Function] Enables the instruction cache.
OCF: Set the OCF (operand cache flush) bit to 1
[Function] Flushes the operand cache
(its contents are not written back to external memory).
WT: Clear the WT (write through) bit to 0
[Function] Set the write-back mode.
OCE: Set the OCE (operand cache enable) bit to 1
[Function] Enables the operand cache.
Store the interrupt mask and set it to level 15 (interrupt disabled)
Read the cache control register 1 (CCR1)
Set the cache control register 1 (CCR1)
Set the interrupt mask
Restore the interrupt mask
Restore the interrupt mask
Figure 2 Example Flow for Settings Up the Cache
R01AN0300EJ0101 Rev. 1.01 Page 5 of 12
Oct. 15, 2010