Specifications

SH7670 Group Example of Cache Memory Setting
R01AN0300EJ0101 Rev. 1.01 Page 3 of 12
Oct. 15, 2010
2. Description of the Sample Application
This sample application employs the instruction cache and operand cache.
2.1 Summary of MCU Functions Used
If the instruction cache and operand cache are enabled (respectively, when the ICE and OCE bits in register CCR1 are
set to 1), whenever an instruction or data in a cacheable area is accessed, the cache is searched to see if it contains the
desired instruction or data. The cache is searched according to the following procedure.
1. A single entry is selected by using bits 10 to 4 of the address used to access memory from CPU and the tag
addresses at the corresponding entry number in all four ways are read out. At this time, the highest-order three bits
of the tag addresses are always cleared to 0.
2. Bits 31 to 11 of the address used to access memory are compared with the tag addresses that have been read out.
Address comparison is with the tag addresses read out from the entries in all four ways.
3. When the result of comparison is a match with a tag address and the selected entry is valid (V = 1), a cache hit is
said to have occurred. When the comparison does not show a match or the selected entry is not valid (V = 0), a
cache miss is said to have occurred.
4. In the case of a cache hit, the long-word (LW) of data at the position in the data array defined by bits 3 and 2 of the
accessed address is read or written.
Table 1 Overview of Caches
Item Description
Capacity Instruction cache: 8 KB
Operand cache: 8 KB
Structure Instructions and data are separated; each cache is 4-way set associative
Cache lock function Ways 2 and 3 can be locked (only in the operand cache)
Line size 16 bytes
Number of entries 128
Write system Write-back and write-through methods are selectable
Replacement method Least-recently-used (LRU) algorithm