Specifications

SH7670 Group Example of Cache Memory Setting
R01AN0300EJ0101 Rev. 1.01 Page 2 of 12
Oct. 15, 2010
1. Introduction
1.1 Specifications
• The instruction cache and the operand cache are enabled and placed in the write-back mode.
1.2 Module Used
• Bus state controller (BSC)
• Cache
1.3 Applicable Conditions
MCU SH7670
Operating Frequency Internal clock: 200 MHz
Bus clock: 66.6 MHz
Peripheral clock: 33.3 MHz
Integrated Development
Environment
Renesas Electronics
High-performance Embedded Workshop Ver.4.03.00
C Compiler Renesas Electronics SuperH RISC engine Family
C/C++ compiler package Ver.9.01 Release 01
Compiler Options Default setting in the High-performance Embedded Workshop
(-cpu=sh2afpu -fpu=single -debug -gbr=auto -global_volatile=0 -opt_range=all
-infinite_loop=0 -del_vacant_loop=0 -struct_alloc=1)
1.4 Related Application Notes
For more information, refer to the following application notes:
• SH7670 Group Example of Initialization